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我正在模拟一个CPU，并且正在使用高级仿真工具来执行此操作。 SystemC是用于这些目的的良好资源。我用两个模块：SystemC模拟应用程序中的问题处理信号
数据路径
内存
CPU数据通路建模为一个独特的高层次的实体，但是下面的代码将肯定比任何其他更好的解释：
以下是datapath.hpp
SC_MODULE(DataPath) {
sc_in_clk clk;
sc_in<bool> rst;
///
/// Outgoing data from memory.
///
sc_in<w32> mem_data;
///
/// Memory read enable control signal.
///
sc_out<sc_logic> mem_ctr_memreadenable;
///
/// Memory write enable control signal.
///
sc_out<sc_logic> mem_ctr_memwriteenable;
///
/// Data to be written in memory.
///
sc_out<w32> mem_dataw; //w32 is sc_lv<32>
///
/// Address in mem to read and write.
///
sc_out<memaddr> mem_addr;
///
/// Program counter.
///
sc_signal<w32> pc;
///
/// State signal.
///
sc_signal<int> cu_state;
///
/// Other internal signals mapping registers' value.
/// ...
// Defining process functions
///
/// Clock driven process to change state.
///
void state_process();
///
/// State driven process to apply control signals.
///
void control_process();
// Constructors
SC_CTOR(DataPath) {
// Defining first process
SC_CTHREAD(state_process, clk.neg());
reset_signal_is(this->rst, true);
// Defining second process
SC_METHOD(control_process);
sensitive << (this->cu_state) << (this->rst);
}
// Defining general functions
void reset_signals();
};
以下是datapath.cpp
void DataPath::state_process() {
// Useful variables
w32 ir_value; /* Placing here IR register value */
// Initialization phase
this->cu_state.write(StateFetch); /* StateFetch is a constant */
wait(); /* Wait next clock fall edge */
// Cycling
for (;;) {
// Checking state
switch (this->cu_state.read()) { // Basing on state, let's change the next one
case StateFetch: /* FETCH */
this->cu_state.write(StateDecode); /* Transition to DECODE */
break;
case StateDecode: /* DECODE */
// Doing decode
break;
case StateExecR: /* EXEC R */
// For every state, manage transition to the next state
break;
//...
//...
default: /* Possible not recognized state */
this->cu_state.write(StateFetch); /* Come back to fetch */
} /* switch */
// After doing, wait for the next clock fall edge
wait();
} /* for */
} /* function */
// State driven process for managing signal assignment
// This is a method process
void DataPath::control_process() {
// If reset signal is up then CU must be resetted
if (this->rst.read()) {
// Reset
this->reset_signals(); /* Initializing signals */
} else {
// No Reset
// Switching on state
switch (this->cu_state.read()) {
case StateFetch: /* FETCH */
// Managing memory address and instruction fetch to place in IR
this->mem_ctr_memreadenable.write(logic_sgm_1); /* Enabling memory to be read */
this->mem_ctr_memwriteenable.write(logic_sgm_0); /* Disabling memory from being written */
std::cout << "Entering fetch, memread=" << this->mem_ctr_memreadenable.read() << " memwrite=" << this->mem_ctr_memreadenable.read() << std::endl;
// Here I read from memory and get the instruction with some code that you do not need to worry about because my problem occurs HERE ###
break;
case kCUStateDecode: /* DECODE */
// ...
break;
//...
//...
default: /* Unrecognized */
newpc = "00000000000000000000000000000000";
} /* state switch */
} /* rst if */
} /* function */
// Resetting signals
void DataPath::reset_signals() {
// Out signals
this->mem_ctr_memreadenable.write(logic_sgm_1);
this->mem_ctr_memwriteenable.write(logic_sgm_0);
}
正如你可以看到我们有一个时钟驱动的过程，处理CPU转换（改变状态）和国家推动的过程，设置信号的CPU。
我的问题是，当我到达###我期望指令被释放内存（你看不到指令，但他们是正确的，内存组件连接到数据路径使用进出信号，你可以在hpp中看到文件）。 记忆使我获得"XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"，因为mem_ctr_memreadenable和mem_ctr_memwriteenable都设置为'0'。 内存模块是为了成为即时组件而编写的。它使用SC_METHOD编写，其sensitive在输入信号（包括读取使能和写入使能）上定义。当mem_ctr_memreadenable信号为'0'时，存储器组件获得"XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"。
为什么是'0'？我重置信号并将该信号设置为'1'。我不明白为什么我保持'0'的读取使能信号。
你能帮我吗？ Thankyou。
你是对的马丁......我没有尝试，但我确信你说的是正确的。我用VHDL编写代码，也知道这个问题在SystemC中也存在（这不是问题，只是一个时间模型）。我不知道为什么我这么固执，没有看到这个愚蠢的问题...我有点惭愧，因为有人问... Thankyou非常... :) – Andry 2011-04-13 15:29:53