在Verilog中处理固定精度的最简单方法是引入一个比例因子并分配足够大的寄存器来保存最大值。例如,如果您知道数字的最大值将是40,并且小数点右侧的精度的三位数字是正确的,则可以将16位的寄存器使用1000的缩放因子。 Verilog处理无符号数字,所以如果值可能是负数,就必须在声明中加上“签名”。 Verilog的可能是:
`define NUMBER_ROWS 100
`define NUMBER_COLS 50
`define MAX_ROW (`NUMBER_ROWS-1)
`define MAX_COL (`NUMBER_COLS-1)
module moveMemory();
reg clk;
reg [15:0] y2shape [`MAX_ROW:0][`MAX_COL:0];
reg [15:0] yfftshift [`NUMBER_ROWS * `NUMBER_COLS:0];
integer rowNumber, colNumber;
always @(posedge clk)
begin
for (rowNumber = 0; rowNumber < `NUMBER_ROWS; rowNumber = rowNumber + 1)
for (colNumber = 0; colNumber < `NUMBER_COLS; colNumber = colNumber + 1)
y2shape[rowNumber][colNumber] <= yfftshift[rowNumber * `NUMBER_COLS + colNumber];
end
endmodule
这对FPGA或仿真项目确定,但对于全定制工作,一个SRAM宏将被用来避免16000个寄存器相关联的裸片面积。对于FPGA实现,您可能已经支付了16K寄存器,或者您可以做一些额外的工作,让合成器将寄存器映射到片内SRAM。
试验台:
//测试代码 整数loadCount,rowShowNumber,colShowNumber; 初始 开始 //初始化阵列与一些数据 为(loadCount = 0; loadCount <(NUMBER_ROWS *
NUMBER_COLS); loadCount = loadCount + 1) yfftshift [loadCount] < = loadCount; clk < = 0;
// Clock the block
#1
clk <= 1;
// Display the results
#1
$display("Y2SHAPE has these values at time ", $time);
for (rowShowNumber = 0; rowShowNumber < `NUMBER_ROWS; rowShowNumber = rowShowNumber + 1)
for (colShowNumber = 0; colShowNumber < `NUMBER_COLS; colShowNumber = colShowNumber + 1)
$display("y2shape[%0d][%0d] is %d ", rowShowNumber, colShowNumber, y2shape[rowShowNumber][colShowNumber]);
end
仿真结果为一个number_rows = 10,NUMBER_COLS = 5
Y2SHAPE has these values at time 2
y2shape[0][0] is 0
y2shape[0][1] is 1
y2shape[0][2] is 2
y2shape[0][3] is 3
y2shape[0][4] is 4
.
.
.
y2shape[9][2] is 47
y2shape[9][3] is 48
y2shape[9][4] is 49
检查[此](http://www.asic-world.com/verilog/memory_fsm1.html)教程找到基本知识。 – Qiu
我经历了那个教程,但我无法在这里使用这个概念。 – jagadish
@jagadish,请分享您迄今为止撰写的Verilog。 – Greg