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我有下面的Verilog代码,为什么我得到“赋值时不兼容的类型” - 赋值“pwmData = 4'b1000;”的错误?我在Active-HDL 9.2中遇到了错误。为什么在Verilog中出现“赋值时不兼容的类型”错误?
module PwmTestbench;
parameter dataWidth = 4;
reg clock, reset, pwmData[3:0], loadPwmData;
wire pwmOut;
Pwm #(.dataWidth(dataWidth)) pwm (
.clk(clock),
.reset(reset),
.data(pwmData),
.load(loadPwmData),
.out(pwmOut)
);
initial begin
clock = 1'b1;
reset = 1'b1;
loadPwmData = 1'b0;
end
always begin
#1 clock = !clock;
end
initial begin
#1 pwmData = 4'b1000; // # Error: VCP2852 pwm_tb.v : (29, 1): Incompatible types at assignment: .pwmData<reg[3:0]> <- 4'b1000<[3:0]bit>.
#1 loadPwmData = 1'b1;
#2 loadPwmData = 1'b0;
#1 reset = 1'b0;
#512 $finish;
end
endmodule
非常感谢你。是一个典型的初学者错误,但我无法发现它。 – user2407434