我正在使用Quartus Prime Pro。
我负责的一个功能,例如:VHDL无法在用户定义的函数中匹配to_unsigned的调用上下文
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
function round_resize (a : unsigned; b : integer) return unsigned is
variable c : signed (a'length - 1 downto 0); --problem child
variable d : signed (b - 1 downto 0);
begin
c := a + to_signed(2**(b-2), a'length);
d := to_unsigned(c(c'length-2 downto (c'length-b-1)));
return d;
end function;
但我得到的错误:
Error(13643): VHDL error at file.vhd(109): can't determine definition of operator ""+"" -- found 0 possible definitions
所以我改变了问题的孩子这样的:
c := to_unsigned(a + to_signed(2**(b-2), a'length), a'length);
但我得到以下错误:
Error(13815): VHDL Qualified Expression error at cpmmod.vhd(110): to_unsigned type specified in Qualified Expression must match signed type that is implied for expression by context
我还可以尝试做什么工作?
那么你可以[尊重类型](https://i.stack.imgur.com/5z9aA.jpg),但它不清楚为什么你这样做。 – user1155120
@ user1155120我真的不明白为什么你不把它放在答案中......而是你只是链接到一个有答案的代码图像!为什么尽管所有这些努力,但仍拒绝发布答案? – JHBonarius