VHDL错误与变量连接相关

Question

我正在写VHDL代码，其中我使用了tempx和tempz作为变量，并尝试将它们连接起来，但我在下面注释的行上有一些错误。建议请做些什么？

的错误是：

Error (10500): VHDL syntax error at ArrayDivider.vhd(53) near text ":="; expecting "(", or "'", or ".", 
Error (10500): VHDL syntax error at ArrayDivider.vhd(53) near text "&"; expecting "(", or "'", or "." 

代码：

------- Array Divider -------- 

library ieee; 
use ieee.std_logic_1164.all; 

----- Entity ----- 

entity ArrayDivider is 
    generic 
    (
     ---- For x/y 
     Nx : integer := 8; --- Number of bits in x 
     Ny : integer := 4 --- Number of bits in y 
    ); 
    port 
    (
     ipx : in std_logic_vector(Nx-1 downto 0); -- Input x --- (Nx-1 downto 0) 
     ipy : in std_logic_vector(Ny-1 downto 0); -- Input y --- (Ny-1 downto 0) 
     opd : out std_logic_vector(Nx-Ny downto 0); -- Quotient --- (Nx-Ny downto 0) 
     opr : out std_logic_vector(Ny-1 downto 0) -- Remainder --- (Ny-1 downto 0) 
    ); 
end ArrayDivider; 

----- Architecture ----- 

Architecture Div of ArrayDivider is 
--- This component will compare ipy with parts of ipx of given bits and --- 
--- generate bits of divident as well as partial subtraction results --- 
--- x = parts of ipx (tempx), y = ipy, op = opd(x) and final z = opr ---  

    component Cmp is 
     generic 
     (
      N : integer := 4 
     ); 
     port 
     (
      x : in std_logic_vector(N-1 downto 0); --- N-1 downto 0 
      y : in std_logic_vector(N-1 downto 0); --- N-1 downto 0 
      z : out std_logic_vector(N-1 downto 0); --- N-1 downto 0 
      op : out std_logic 
     ); 
    end Component; 
    variable tempx : std_logic_vector(Ny-1 downto 0) := ipx(Nx-1 downto Nx-Ny); --- (Ny-1 downto 0) (Nx-1 downto Nx-Ny) 
    variable tempz : std_logic_vector(Ny-1 downto 0); --- (Ny-1 downto 0) 
begin 
    lup: 
     for a in Nx-Ny downto 0 generate --- Nx-Ny downto 0 
     begin   
    Cmpa: Cmp generic map(Ny) port map(tempx, ipy, tempz, opd(a)); --- (Ny) 
    grea: 
      if(a > 0) generate 
       tempx := tempz(Ny-2 downto 0) & ipx(a-1); --- (Ny-2 downto 0) 
      end generate grea; 
    zero: 
      if(a = 0) generate 
       opr <= tempz; 
      end generate zero; 
     end generate lup; 
end Div; 

Answer 1

因为你没有使用过程中，你应该使用信号，而不是变量tempx和tempz。然后，您的行53必须看起来如下：

tempx <= tempz(Ny-2 downto 0) & ipx(a-1); 

但是，可能使用过程更有意义。那么你必须实现你的cmp组件作为一个过程（在下面的例子中没有做）。该过程可能如下所示：

... 
end Component; 
begin 

div_proc: process(ipy, ipx) 
    variable tempx : std_logic_vector(Ny-1 downto 0) ; 
    variable tempz : std_logic_vector(Ny-1 downto 0); 
begin 
    lup: 
     for a in 1 downto 0 loop   
    -- Cmpa: Cmp generic map(Ny) port map(tempx, ipy, tempz, opd(a)); 
     grea: 
      if(a > 0) then 
       tempx := tempz(Ny-2 downto 0) & ipx(a-1); 
      end if; 
     zero: 
      if(a = 0) then 
      opr <= tempz; 
      end if; 
    end loop; 
end process div_proc; 
...