任何人都可以帮我弄清楚我的VHDL代码有什么问题吗?下面是代码:FF /闩锁和其他警告
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity main is
port(
--50MHz clock
cp : in std_logic;
--reset signal
reset : in std_logic;
--PS/2 data and clock lines
ps2d, ps2c : in std_logic;
--7-segment display segments
segments : out std_logic_vector (7 downto 0);
--anode control
an : out std_logic_vector (3 downto 0);
--data out to LEDs
dout : out std_logic_vector (7 downto 0)
);
end main;
architecture Behavioral of main is
--data from keyboard entity (scancode)
signal data : std_logic_vector (7 downto 0);
--7 segments of display
signal segReg, segNext : std_logic_vector (6 downto 0);
signal tickDone : std_logic;
begin
--just entity that reads PS/2 keyboard data
--rx_done is tick (20 ns)
S1: entity keyboard port map (cp => cp, ps2d => ps2d, ps2c => ps2c,
rx_done => tickDone, dout => data);
dout <= data;
an <= "1110";
segments(6 downto 0) <= segReg;
--turn off dot
segments(7) <= '1';
process (cp, reset)
begin
if reset = '1' then
segReg <= (others => '0');
elsif rising_edge (cp) then
segReg <= segNext;
end if;
end process;
process (tickDone, segReg)
begin
segNext <= segReg;
if tickDone = '1' then
if data = x"16" then
--number 1
segNext <= "1001111";
elsif data = x"1E" then
--number 2
segNext <= "0010010";
elsif data = x"26" then
--number 3
segNext <= "0000110";
elsif data = x"25" then
--number 4
segNext <= "1001100";
else
segNext <= "1111111";
end if;
end if;
end process;
end Behavioral;
当我尝试合成它/生成编程文件,我得到这些警告:
WARNING:Xst:819 - "C:/VHDL_projekti/PS2K/main.vhd" line 48: The following signals are missing in the process sensitivity list:
WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
WARNING:Xst:1710 - FF/Latch <segReg_0> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_1> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_2> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_3> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_4> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_5> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1710 - FF/Latch <segReg_0> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_1> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_2> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_3> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_4> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_5> (without init value) has a constant value of 0 in block <main>.
WARNING:Par:288 - The signal reset_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
WARNING:PhysDesignRules:367 - The signal <reset_IBUF> is incomplete. The signal
有人可以帮助我?我一直在看代码,我没有看到任何错误,但显然我做错了什么。
1)“以下信号在处理敏感度列表中丢失”这是Xilinx ISE错误吗?我不明白为什么我会在第48行的进程灵敏度列表中需要任何其他信号...
2)“由于其他FF/Latch调整,在块中具有恒定值0”OK,什么是我做错了?我不想使用锁存器......
3)“信号reset_IBUF没有负载,PAR不会尝试路由此信号。”这是什么意思?我的重置信号有什么问题?为什么它不完整?
此代码是我尝试在Spartan 3入门板上使用PS/2键盘。实体“键盘”进行读取并且它正常工作(当我单独测试时,我在dout信号上得到正确的扫描码(我在LED上看到它))。 rx_done是tick(20ns),表示扫描码已被成功读取。
所以我只想看看能否以某种方式识别扫描码(在我的第二个过程中,我正在比较数据信号并将正确的值输入到segNext信号)并在7段显示器上显示某些内容。当我得到这个工作,然后我会实现正确的行为(检测所有的扫描代码,额外的键和键和关键事件)。
我不知道如果我需要别的什么形容,如果我不请给我留下了评论:)
感谢您的帮助!!!!
编辑:编辑的代码(添加数据的敏感性列表和别的if语句):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity main is
port(
--50MHz clock
cp : in std_logic;
--reset signal
reset : in std_logic;
--PS/2 data and clock lines
ps2d, ps2c : in std_logic;
--7-segment display segments
segments : out std_logic_vector (7 downto 0);
--anode control
an : out std_logic_vector (3 downto 0);
--data out to LEDs
dout : out std_logic_vector (7 downto 0)
);
end main;
architecture Behavioral of main is
--data from keyboard entity (scancode)
signal data : std_logic_vector (7 downto 0);
--7 segments of display
signal segReg, segNext : std_logic_vector (6 downto 0);
signal tickDone : std_logic;
begin
--just entity that reads PS/2 keyboard data
--rx_done is tick (20 ns)
S1: entity keyboard port map (cp => cp, ps2d => ps2d, ps2c => ps2c,
rx_done => tickDone, dout => data);
dout <= data;
an <= "1110";
segments(6 downto 0) <= segReg;
--turn off dot
segments(7) <= '1';
process (cp, reset)
begin
if reset = '1' then
segReg <= (others => '0');
elsif rising_edge (cp) then
segReg <= segNext;
end if;
end process;
process (tickDone, segReg, data)
begin
if tickDone = '1' then
if data = x"16" then
--number 1
segNext <= "1001111";
elsif data = x"1E" then
--number 2
segNext <= "0010010";
elsif data = x"26" then
--number 3
segNext <= "0000110";
elsif data = x"25" then
--number 4
segNext <= "1001100";
else
segNext <= "1111111";
end if;
else
segNext <= segReg;
end if;
end process;
end Behavioral;
不幸的是,这些修改后,我仍然有这样的警告:
WARNING:Xst:1710 - FF/Latch <segReg_0> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_1> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_2> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_3> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_4> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_5> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_6> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <segReg_0> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_1> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_2> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_3> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_4> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_5> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Par:288 - The signal reset_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
谢谢!模拟完成后,我意识到tickDone从未被驱动为'1'。在检查键盘实体后,我注意到我在我的FSM中犯了错字(我正在跳过tickDone被驱动为'1'的最后状态)...再次感谢:) – xx77aBs 2012-03-15 11:51:24