我想在时钟逻辑中创建3个信号。带3个信号的计数器
8s
7s ----- create working signal
6s
5s
4s
3s
2s
1s ----- create timeout signal
0s ----- create finish signal
always @(posedge CLK_1K or posedge signal_count) begin
slot_count = 0;
data_finish = 0;
timeout = 0;
working = 0;
if (signal_count) begin
slot_count <= 1;
counter <= 8;
end else if (counter > 0) begin
counter = counter - 1;
if (counter == 7) begin
working = 1;
end else if (counter == 1) begin
timeout = 1;
end else if(counter == 0) begin
data_finish = 1;
end
end
end
什么做了:
- 在模拟试验是正常的。
- 下载到设备正常工作...
我下一步该做什么?谢谢....
你能更具体吗?你的代码是在模拟中工作,而不是在设备上工作?还是你收到综合错误? –