如果控制语句后的Verilog语法错误

Question

我想在我的几个不同的选择模块的Verilog中创建一个零检查模块。

module check_zero (input [63:0] a, b, [1:0] select, output reg [63:0] out); 

if ((a[51:0] == 0) && (b[51:0] == 0)) begin 
      out <= 0; 
      state <= done; 

end else if (a[51:0]==0 && select==0) begin 
     out <= b; 
      state <= done; 
end else if (b[51:0]==0 && select==0) begin 
     out <= a; 
      state <= done; 

end else if (a[51:0]==0 && select==1) begin 
     out[63] <= ~b[63]; 
     out[62:0] <= ~b[62:0]; 
      state <= done; 
end else if (b[51:0]==0 && select==1) begin 
     out <= a; 
      state <= done; 

end else if (a[51:0]==0 && select==2) begin 
     out <= 0; 
      state <= done; 
end else if (b[51:0]==0 && select==2) begin 
     out <= 0; 
      state <= done; 
end 

end else if (a[51:0]==0 && select==3) begin 
     out <= 0; 
      state <= done; 
end else if (b[51:0]==0 && select==3) begin 
     out[63] <= 1; 
      out[62:52] <= 2047; 
      out[51] <= 1; 
      out[50:0] <= 0; 
      state <= done; 
end 
endmodule 

我正在2级中的错误的ModelSim： 1.（视频博客-13069）的语法错误，意想不到 '< =' 在第2行以后出 2.（视频博客-13205）语法中的范围中发现错误接下来，是否有一个缺少'::'

Answer 1

你有一个额外的“结束”那里。

end else if (b[51:0]==0 && select==2) begin 
out <= 0; 
state <= done; 
end // this is extra, delete it