VHDL如果语句的语法错误

我有以下代码：VHDL如果语句的语法错误

process(value_counter, hex5_value) 
    begin 
     if(value_counter <= x"0F") then 
      with value_counter select hex4 <= --error on this line 
      "0111111" when x"00", 
      "0000110" when x"01", 
      "1011011" when x"02", 
      "1001111" when x"03", 
      "1100110" when x"04", 
      "1101101" when x"05", 
      "1111101" when x"06", 
      "0000111" when x"07", 
      "1111111" when x"08", 
      "1101111" when x"09", 
      "1110111" when x"0A", 
      "1111100" when x"0B", 
      "0111001" when x"0C", 
      "1011110" when x"0D", 
      "1111001" when x"0E", 
      "1110001" when x"0F"; 

      hex5<="0111111"; 
     elsif(value_counter > x"0F") then 
      with value_counter mod 10 select hex4 <= 
      "0111111" when x"00", 
      "0000110" when x"01", 
      "1011011" when x"02", 
      "1001111" when x"03", 
      "1100110" when x"04", 
      "1101101" when x"05", 
      "1111101" when x"06", 
      "0000111" when x"07", 
      "1111111" when x"08", 
      "1101111" when x"09", 
      "1110111" when x"0A", 
      "1111100" when x"0B", 
      "0111001" when x"0C", 
      "1011110" when x"0D", 
      "1111001" when x"0E", 
      "1110001" when x"0F"; 

      with hex5_value select hex5 <= 
      "0111111" when x"00", 
      "0000110" when x"01", 
      "1011011" when x"02", 
      "1001111" when x"03", 
      "1100110" when x"04", 
      "1101101" when x"05", 
      "1111101" when x"06", 
      "0000111" when x"07", 
      "1111111" when x"08", 
      "1101111" when x"09", 
      "1110111" when x"0A", 
      "1111100" when x"0B", 
      "0111001" when x"0C", 
      "1011110" when x"0D", 
      "1111001" when x"0E", 
      "1110001" when x"0F"; 
     end if; 
end process;

但运行它时，我得到的指示线以下错误：Error (10500): VHDL syntax error at xxx near text "with"; expecting "end", or "(", or an identifier ("with" is a reserved keyword), or a sequential statement。任何人都知道这是什么原因造成的，以及我如何能够合法和等同地重写它？

来源

2013-01-25 John Roberts

你真正的意思“国防部10”，而不是“国防部16 “？ –

“正确的”答案是一个过程中的CASE陈述或组合区域（即在过程之外）中的“with ... select”。

但是，如果你创建了16七段显示值的常量数组，并简单地索引的数组，你将有更加美好VHDL：

subtype seven_seg is std_logic_vector(6 downto 0); 

constant decode : array 0 to 15 of seven_seg := (
      "0111111", "0000110", "1011011", "1001111", 
      "1100110", "1101101", "1111101", "0000111", 
      "1111111", "1101111", "1110111", "1111100", 
      "0111001", "1011110", "1111001", "1110001"); 

    process(value_counter, hex5_value) 
     begin 
      if value_counter <= x"0F" then 
       hex4 <= decode(to_integer(value_counter(3 downto 0))); 
       hex5 <= decode(0); 
      -- elsif value_counter > x"0F" then 
      -- surely this "elsif" is unnecessary! 
      else 
       hex4 <= decode(to_integer(value_counter(7 downto 4))); 
       hex5 <= decode(to_integer(hex5_value(3 downto 0))); 
      end if; 
    end process;

来源

2013-01-25 15:09:24

'with'的信号分配是一个并发语句。所以它在一个流程中无效。 '案件'可以做到这一点。但是当案件变得很安静时，检查时间分析的结果。

有关更多语法信息，请参阅this link。

来源

2013-01-25 14:44:10 vermaete

VHDL如果语句的语法错误

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