七段码上的十六进制数字

Question

我需要设计一个由四个4位寄存器组成的库，其内容显示在七段显示器上。所以，基本上只是在7段上显示4个十六进制数字。输出在每个时钟周期自行切换。我为此使用了Basys2板。这是我到目前为止......

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 

entity Register_Bank is 
port(x: in std_logic_vector(3 downto 0); 
     disp_en: out std_logic_vector(3 downto 0); 
     z: out std_logic_vector(7 downto 0); 
     ck,reset: in std_logic); 
end Register_Bank; 

architecture Behavioral of Register_Bank is 

Type my_state is(s0,s1,s2,s3); 
Signal n_s: my_state; 
Signal ck_div: std_logic; 
Signal temp,temp1,temp2,temp3,temp0,temp_main: std_logic_vector(0 to 3); 
Signal R0,R1,R2,R3 : std_logic_vector(3 downto 0); 

begin 

-- 
process(temp_main) 
begin 
case temp_main is 
    when "0000" => z <= "00000011"; 
    when "0001" => z <= "10011111"; 
    when "0010" => z <= "00100101"; 
    when "0011" => z <= "00001101"; 
    when "0100" => z <= "10011001"; 
    when "0101" => z <= "01001001"; 
    when "0110" => z <= "01000001"; 
    when "0111" => z <= "00011111"; 
    when "1000" => z <= "00000001"; 
    when "1001" => z <= "00001001"; 
    when "1010" => z <= "00010001"; 
    when "1011" => z <= "11000001"; 
    when "1100" => z <= "01100011"; 
    when "1101" => z <= "10000101"; 
    when "1110" => z <= "01100001"; 
    when "1111" => z <= "01110001"; 
    when others => null; 

--temp3 <= x<3>; 
--temp2 <= x<2>; 
--temp1 <= x<1>; 
--temp0 <= x<0>; 

--wiring the register contents to outputs 
temp3 <= R3; 
temp2 <= R2; 
temp1 <= R1; 
temp0 <= R0; 

--state machine for TMD 
Process(x,ck_div) 
begin 
if ck_div ='1' and ck_div'event then 
case n_s is 
    when s0 => 
     temp <= x<0>; 
     disp_en <= "0111"; 
     n_s <= s1; 
    when s1 => 
     temp <= x<1>; 
     disp_en <= "1011"; 
     n_s <= s2; 
    when s2 => 
     temp <= x<2>; 
     disp_en <= "1101"; 
     n_s <= s3; 
    when s3 => 
     temp <= x<3>; 
     disp_en <= "1110"; 
     n_s <= s0; 
end case; 
end if; 
end process; 

-- clock division 
process(ck) 
variable count: integer; 
begin 
if ck ='1' and ck'event then 
    if reset ='1' then 
     count := 0; 
     ck_div <= '0'; 
    elsif reset ='0' then 
     if count = 999999 then 
      ck_div <= not ck_div; 
      count := 0; 
     else 
      count := count + 1; 
     end if; 
    end if; 
end if; 
end process;  

end Behavioral; 

我知道逻辑关闭，也有语法错误。我需要帮助，试图调试这个。我非常感谢帮助！

Answer 1

如果您尝试提交至少在语法上正确的代码，那将会很不错。如果你运行它的ModelSim（或通过Sigasi编辑器），你会看到两个琐碎的语法错误：

• 缺少两个“END”关键字
• 载体片使用圆括号：x(1)，不是菱形x<1>

只有在解决这个问题之后，您才能处理您设计的行为。

有一些代码，你可能想在这里看看：http://www.sigasi.com/content/7-segment-display

Answer 2

首先，不要使用ck_div作为时钟。改变你的代码，使其变高了一个滴答声在1000000然后更改主过程使用该信号作为使：

if rising_edge(clk) and ck_div = '1' then 

这样可以使你的设计完全同步到一个时钟，这意味着该工具找到生活变得更加容易 - 而且任何可以让工具变得更轻松的事情都是设计师的一个胜利。