如何将记录写入内存并将其恢复为VHDL？

Question

在VHDL中的伪代码我想达到的目的是：

type tTest is record 
    A : std_logic_vector(3 downto 0); 
    B : std_logic_vector(7 downto 0); 
    C : std_logic_vector(0 downto 0); 
end record tTest; 
. . . 
signal sTestIn  : tTest; 
signal sMemWrData : std_logic_vector(fRecordLen(tTest)-1 downto 0); 
signal sMemRdData : std_logic_vector(fRecordLen(tTest)-1 downto 0); 
signal sTestOut  : tTest; 
. . . 
sMemWrData <= fRecordToVector(sTestIn); 
-- At some point sMemRdData gets the data in sMemWrData... 
sTestOut <= fVectorToRecord(sMemRdData); 

fRecordLen是直接从型和fRecordToVector和fVectorToRecord是希望自我解释返回记录的聚集长度的假想功能。目标是可合成的代码，不会产生任何额外的逻辑。我发布当前的解决方案作为进一步澄清操作的答案。然而，这是非常尴尬的方法，由于锅炉板代码的数量，我不认为它是一个可行的解决方案。

我知道record introspection proposal但并不屏住呼吸，甚至提出的方法似乎非常繁琐。

我已经放弃了一个完全一般的解决方案的希望，所以一些让步是可以接受的。例如，只允许记录中的std_logic_vectors并使用几个函数/过程调用。但是，避免使用任何必须手动或根据每个记录进行外部脚本调整的任何锅炉代码将是非常好的。另外，如果有任何可以直接输入/输出记录并且达到相同的Verilog/SystemVerilog包装，则非常欢迎指针。

Answer 1

这是一种实现要求的方法。评论中有缺点/改进的想法。

library ieee; 
use ieee.std_logic_1164.all; 
package TestPck is 
    type tTest is record 
     A : std_logic_vector(3 downto 0); 
     B : std_logic_vector(7 downto 0); 
     C : std_logic_vector(0 downto 0); 
    end record tTest; 
    procedure pSliceToFrom (
     signal vec_to : out std_logic_vector; 
     signal vec_from : in std_logic_vector; 
     position  : inout integer 
    ); 
end package TestPck; 

package body TestPck is 
    procedure pSliceToFrom (
    signal vec_to : out std_logic_vector; 
    signal vec_from : in std_logic_vector; 
    position  : inout integer 
    ) is 
    begin 
    vec_to <= vec_from(position-1 downto position-vec_to'length); 
    position := position-vec_to'length; 
    end pSliceToFrom; 
end package body TestPck; 

library ieee; 
use ieee.std_logic_1164.all; 
use work.TestPck.all; 

entity tb is 
end entity tb; 

architecture sim of tb is 
    signal sTestIn  : tTest; 
    -- How to create this constant in the package, 
    -- i.e. without needing the signal? 
    constant cTestLength : integer := sTestIn.A'length + sTestIn.B'length + sTestIn.C'length; 
    signal sMemWrData : std_logic_vector(cTestLength-1 downto 0); 
    signal sMemRdData : std_logic_vector(cTestLength-1 downto 0); 
    signal sTestOut  : tTest; 
begin 
    -- How to make this without needing to know what 
    -- is inside tTest? 
    sMemWrData <= sTestIn.A & sTestIn.B & sTestIn.C; 
    -- Memory, Fifo, communication link, doesn't matter... 
    sMemRdData <= sMemWrData after 5 ns; 
    -- How to get the data back without needing this 
    -- process (and the procedure)? 
    slice_data_to_item : process (all) is 
    variable vPosition : integer := 0; 
    begin 
    vPosition := cTestLength; 
    pSliceToFrom(sTestOut.A, sMemRdData, vPosition); 
    pSliceToFrom(sTestOut.B, sMemRdData, vPosition); 
    pSliceToFrom(sTestOut.C, sMemRdData, vPosition); 
    end process slice_data_to_item; 

process is 
    begin 
     wait for 10 ns; 
     sTestIn <= (x"E", x"A7", "1"); 
     wait for 10 ns; 
     sTestIn <= (x"7", x"AC", "0"); 
     wait; 
    end process; 
end architecture sim; 

Answer 2

将数据从矢量（线性数组）转换为记录的一种方法是通过使用聚合。

library ieee; 
use ieee.std_logic_1164.all; 

package TestPck is 
    subtype A is std_logic_vector (12 downto 9); 
    subtype B is std_logic_vector (8 downto 1); 
    subtype C is std_logic_vector (0 downto 0); 
    constant ABC_len: natural := A'length + B'length + C'length; 
    type tTest is record 
     A: std_logic_vector (A'RANGE); 
     B: std_logic_vector (B'RANGE); 
     C: std_logic_vector (C'RANGE); 
    end record tTest; 
    type tTests is array (natural range <>) of tTest; 
end package TestPck; 

library ieee; 
use ieee.std_logic_1164.all; 
use work.TestPck.all; 

entity tb is 
end entity tb; 

architecture sim of tb is 
    signal sTestIn:  tTest; 
    signal sMemWrData:  std_logic_vector(ABC_len - 1 downto 0); 
    signal sMemRdData:  std_logic_vector(ABC_len - 1 downto 0); 
    signal sTestOut:  tTest; 
    constant tests:  tTests (0 to 1) := 
      (0 => (x"E", x"A7", "1"), 1 => (x"7", x"AC", "0")); 
begin 
    sMemWrData <= sTestIn.A & sTestIn.B & sTestIn.C; 
    sMemRdData <= sMemWrData after 5 ns; 
    sTestOut <= 
     tTest'(sMemRdData(A'range), sMemRdData(B'range), SMemRdData(C'range)); 
process is 
    begin 
     wait for 10 ns; 
     sTestIn <= tests(0); 
     wait for 10 ns; 
     sTestIn <= tests(1); 
     wait for 10 ns; 
     wait; 
    end process; 
end architecture sim; 

合格表达集合体定义为t检验记录的与位置相关联，其被分配给该记录类型sTestOut的值。

这给出：

因此可以使用级联用于组装的矢量值（或在-2008的聚集体），并使用聚合为合格的表达式来sMemRdData转移到sTestOut。

如果您还没有计划宣布的A，B或C亚型的对象，你可以声明为整数亚型：

library ieee; 
use ieee.std_logic_1164.all; 

package TestPck is 
    subtype A is natural range 12 downto 9; 
    subtype B is natural range 8 downto 1; 
    subtype C is natural range 0 downto 0; 
    constant ABC_len: natural := A'left + 1; 
    type tTest is record 
     A: std_logic_vector (A); 
     B: std_logic_vector (B); 
     C: std_logic_vector (C); 
    end record tTest; 
    type tTests is array (natural range <>) of tTest; 
end package TestPck; 

library ieee; 
use ieee.std_logic_1164.all; 
use work.TestPck.all; 

entity tb is 
end entity tb; 

architecture sim of tb is 
    signal sTestIn:  tTest; 
    signal sMemWrData:  std_logic_vector(ABC_len - 1 downto 0); 
    signal sMemRdData:  std_logic_vector(ABC_len - 1 downto 0); 
    signal sTestOut:  tTest; 
    constant tests:  tTests (0 to 1) := 
      (0 => (x"E", x"A7", "1"), 1 => (x"7", x"AC", "0")); 
begin 
    sMemWrData <= sTestIn.A & sTestIn.B & sTestIn.C; 
    sMemRdData <= sMemWrData after 5 ns; 
    sTestOut <= 
     tTest'(sMemRdData(A), sMemRdData(B), SMemRdData(C)); 
process is 
    begin 
     wait for 10 ns; 
     sTestIn <= tests(0); 
     wait for 10 ns; 
     sTestIn <= tests(1); 
     wait for 10 ns; 
     wait; 
    end process; 
end architecture sim; 

这可能是更容易一些阅读。它会产生上面相同的波形。