Verilog代码仿真错误：-unresolved参照rising_edge（CLK）

Question

我已经以Verilog设计的ALU：

module ALU (
output reg overflow_16_1, // overflow flag used for 16 bit addition and subtraction 
output reg overflow_16_2, // overflow flag used for 16 bit addition and subtraction 
output reg overflow_16_3, // overflow flag used for 16 bit addition and subtraction 
output reg overflow_16_4, // overflow flag used for 16 bit addition and subtraction 
output reg overflow_32_1, // overflow flag used for 32 bit addition and subtraction 
output reg overflow_32_2, // overflow flag used for 32 bit addition and subtraction 
output reg overflow_64, // overflow flag used for 64 bit addition and subtraction 
output reg[63:0] z,  // output of the ALU 
input [63:0] X,   // 64 bit input of the ALU 
input [63:0] Y,   // 64 bit input of the ALU 
input [1:0] Operations, //to indicate the operation to be performed 
input [2:0] Modes,  // to indicate the word size of the operation 
input clk 
); 


always@(posedge(clk)) 
begin 

case(Modes) 

    3'b 000:    //if the Mode is 000 perform one 64 bit Operation 
     case(Operations) 
     2'b 00:  

      {overflow_64,z} = {1'b0,X} + {1'b0,Y}; //if Operation == 00 perform addition 

     2'b 01: 

     {overflow_64,z} = {1'b0,X}-{1'b0,Y}; //if Operation == 01 perform subtraction 

     2'b 10: if (X<=Y)     ////if Operation == 10 perform comparison 
      begin 
       z = Y;       //if Y is greater o/p is Y 
       end 
       else 
       begin 
       z=X;        //if X is greater o/p is X 
      end 
     default: $display("error in selecting operation"); // if the operation selection is invalid 
      endcase 


    3'b 001: case(Operations) // if the Mode == 001 perform two 32 bit Operations 
     2'b 00: 
     begin 
     {overflow_32_1,z[63:32]}={1'b0,X[63:32]}+{1'b0,Y[63:32]}; //if Operation == 00 perform addition 
     {overflow_32_2,z[31:0]}={1'b0,X[31:0]}+{1'b0,Y[31:0]}; 
     end 
     2'b 01: 
     begin 
     {overflow_32_1,z[63:32]}={1'b0,X[63:32]}-{1'b0,Y[63:32]}; //if Operation == 01 perform subtraction 
     {overflow_32_2,z[31:0]}= {1'b0,X[31:0]}-{1'b0,Y[31:0]}; 
     end 

     2'b 10:begin 
      if (X<=Y)          ////if Operation == 10 perform comparison 
      begin 
      z[63:32]= Y[63:32];     //if Y is greater o/p is Y  
      z[31:0]= Y[31:0]; 
      end 
      else 
      begin 
      z[63:32]= X[63:32];     //if X is greater o/p is X 
      z[31:0]= X[31:0]; 
      end 
      end 
      default: $display("error in selecting the Modes"); // if the operation selection is invalid 


    endcase 

    3'b 010: case(Operations)   // if the Mode == 010 perform four 16 bit Operations 
    2'b 00: begin 

     {overflow_16_1,z[63:48]}= {1'b0,X[63:48]}+ {1'b0,Y[63:48]}; //if Operations == 00 perform addition 
     {overflow_16_2,z[47:32]}= {1'b0,X[47:32]}+ {1'b0,Y[47:32]}; 
     {overflow_16_3,z[31:16]}= {1'b0,X[31:16]}+ {1'b0,Y[31:16]}; 
     {overflow_16_4,z[15:0]}= {1'b0,X[15:0]}+ {1'b0,Y[15:0]}; 
     end 
     2'b 01:begin 
     {overflow_16_1,z[63:48]}= {1'b0,X[63:48]}- {1'b0,Y[63:48]}; // if Operations == 01 perform subtraction 
     {overflow_16_2,z[47:32]}= {1'b0,X[47:32]}- {1'b0,Y[47:32]}; 
     {overflow_16_3,z[31:16]}= {1'b0,X[31:16]}- {1'b0,Y[31:16]}; 
     {overflow_16_4,z[15:0]}= {1'b0,X[15:0]}- {1'b0,Y[15:0]}; 
     end 

     2'b 10:begin 
      if (X<= Y)      // if Operations == 10 perform comparison 
      begin 
     z[63:48]= Y[63:48];    // if Y is greater then o/p is Y 
     z[47:32]= Y[47:32]; 
     z[31:16]= Y[31:16]; 
     z[15:0]= Y[15:0]; 
     end 
      else 
      begin 
     z[63:48]= X[63:48];    //else o/p is X 
     z[47:32]= X[47:32]; 
     z[31:16]= X[31:16]; 
     z[15:0]= X[15:0]; 
      end 
     end 

     default: $display("error in selecting the operation"); // if the operation selection is invalid 

    endcase 
    default: $display("error in selecting the Modes");  // if the word size selection is invalid 

endcase 

end 


endmodule 

我想要的行为模型是在输入的变化，并在过渡敏感o/p在时钟的上升沿之后发生。 起初我写的代码，如..

always(*) 
begin 
if(rising_edge(clk)) 
begin 
.. 

但同时模拟说悬而未决参考

rising_edge(clk) 

我怎样才能解决这个错误我得到了错误？或上面的代码是好的？

请回答

Answer 1

上面的代码（总是@）是正确的。 每当时钟切换时，计算正确的操作，这是重要的。

您的困惑可能源于这样一个事实：通过这样做，看起来输出“奇迹般”出现在时钟边缘，而您没有看到组合活动。实际上它确实发生，但在评估时。

这是最紧凑的编码可能。

什么您最初计划可以做到的，但必须在这个简单的例子可以分为两个过程，如：

always@(*) begin 
    q_next =~q; 
end 

always @(posedge clk) begin 
    // Please add a reset condition 
    q <= q_next; 
end 

这是完全等同于

always@(posedge clk) begin 
    // Please add a reset condition 
    q <= ~q; 
end 

在这样的情况下这个我没有看到拆分代码的理由，因为很明显整个过程正在生成同步信号。写状态机，必须在其中产生一些组合控制信号的时候，但是这是一个不同的主题