6
通过使用cosmiac教程13 http://www.cosmiac.org/tutorial_13.html和ISE 10.1，pdf文件显示了如何生成图像，并且您可以通过单击第一个.zip文件来下载该项目。在该项目结束时，它说...现在尝试以类似的方法流式传输一个小视频。 注意：需要适当修改Matlab文件以获取像素信息，并使用reader.vhd获取已使用的视频规格。还需要获得仅使用颜色（可以用Spartan-3E板代表）的视频，以便获得清晰的输出。如何在斯巴达3e fpga流小视频？
我的问题是...如果我有matlab .coe文件（视频帧），是否使用单端口ram（核心存储器生成器中的哪种类型的ram）来流式传输小视频？以及如何修改下面的读者？可以说我从2帧开始（2张图片）。我想让它像一个视频一样背对背，或者在另一个背景（比较容易）的顶部显示它。
事情要记住..vhdl编程语言，Xilinx是任何版本（我可以更新），Xilinx Impact。
---------------------------------------------------------------------------------
-- File Name: reader.vhd
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity reader is
Port (clk, reset : in STD_LOGIC;
row : in STD_LOGIC_VECTOR (9 downto 0);
col : in STD_LOGIC_VECTOR (9 downto 0);
addr : out STD_LOGIC_VECTOR (15 downto 0);
ennormal, enencryp : out std_logic;
datain : in STD_LOGIC_VECTOR (2 downto 0);
dataout : out STD_LOGIC_VECTOR (2 downto 0));
end reader;
architecture Behavioral of reader is
constant vtop : integer := 128;
constant vbottom : integer := 351;
constant htop1 : integer := 64;
constant hbottom1 : integer := 287;
constant htop2 : integer := 352;
constant hbottom2 : integer := 575;
signal addr_normal : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal addr_encryp : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
signal en_normal : std_logic := '0';
signal en_encryp : std_logic := '0';
begin
ens : process (clk, reset)
begin
if reset = '1' then
en_normal <= '0';
en_encryp <= '0';
elsif clk'event and clk='1' then
if (row >= vtop) and (row <= vbottom) then
if (col >= htop1) and (col <= hbottom1) then
en_normal <= '1';
en_encryp <= '0';
elsif (col >= htop2) and (col <= hbottom2) then
en_normal <= '0';
en_encryp <= '1';
else
en_normal <= '0';
en_encryp <= '0';
end if;
else
en_normal <= '0';
en_encryp <= '0';
end if;
end if;
end process ens;
c_normal: process (clk, reset)
begin
if reset = '1' then
addr_normal <= (others => '0');
elsif clk'event and clk='1' then
if en_normal = '1' then
if addr_normal = 50175 then
addr_normal <= (others => '0');
else
addr_normal <= addr_normal + 1;
end if;
end if;
end if;
end process c_normal;
c_encryp: process (clk, reset)
begin
if reset = '1' then
addr_encryp <= (others => '0');
elsif clk'event and clk='1' then
if en_encryp = '1' then
if addr_encryp = 50175 then
addr_encryp <= (others => '0');
else
addr_encryp <= addr_encryp + 1;
end if;
end if;
end if;
end process c_encryp;
addr <= addr_normal when (en_normal = '1') else addr_encryp;
dataout <= datain;
ennormal <= en_normal;
enencryp <= en_encryp;
end Behavioral;