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我正在写矩阵转置的代码在VHDL我正在输入行主要和每个时钟周期的矩阵的一个元素，我存储数据列主要格式之后，我发送临屋区数据以coloumn格式逐个元素每个时钟周期输出。其代码如下它是正确模仿，但后期合成结果是不正确的，谁能plz帮助如何合成代码以获得正确的结果后综合模拟得到错误的结果
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity Matrix_Trans_Sysgen is
generic(n: integer :=3);
port (my_clk : in std_logic;
my_ce : in std_logic;
input_matrix : in std_logic_vector(5 downto 0);
output_matrix : out std_logic_vector(5 downto 0)
);
end Matrix_Trans_Sysgen;
architecture Behavioral of Matrix_Trans_Sysgen is
type t1 is array (natural range<>) of std_logic_vector(5 downto 0);
signal a : t1((n*n)-1 downto 0) :=(others => (others =>'0'));
signal output_there : std_logic :='0';
signal x : integer range 0 to 2*n :=0;
signal y : integer range 0 to 2*n :=0;
signal z : integer range 0 to 2*n*n :=0;
begin
----- Process to take all input_matrix into array
process(my_clk,input_matrix,x,y)
begin
if(x < n) then
if(y < n) then
if(rising_edge(my_clk)) then
a(y*n+x) <= input_matrix;
y <= y+1;
end if;
else
x<=x+1;
y<=0;
end if;
else
output_there <= '1';
end if;
end process;
----- Process to send all output elements through port
process(my_clk,z,output_there)
begin
if (output_there = '1') then
if(z < n*n) then
if(rising_edge(my_clk)) then
output_matrix <= a(z);
z<=z+1;
end if;
end if;
end if;
end process;
end Behavioral;
感谢和问候
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