当我试图模拟我的代码时，“达到了迭代限制”

Question

我试图在VHDL中实现Booth算法，已经运行“纸张测试”，代码显然可以工作，但是当我模拟它时，我不是得到欲望的结果...然后我替换代码做一个A-Shift来测试，但是当我模拟我的代码时，我得到这个错误：

错误（可压缩）：（vsim-3601）迭代在时间180 ns达到限制5000。

我只是替换这一行：P := STD_LOGIC_VECTOR(unsigned(P) SRA 1);

对于这一点：P := P(16) & P(16 downto 1);

这是代码大气压：

LIBRARY IEEE; 
    USE IEEE.STD_LOGIC_1164.ALL; 
    USE IEEE.STD_LOGIC_UNSIGNED.ALL; 

ENTITY algor_booth IS 
    PORT(oper1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); 
     oper2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); 
     sel : IN STD_LOGIC; 
     result : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) 
      ); 
END ENTITY; 

ARCHITECTURE algor OF algor_booth IS 
BEGIN 
    PROCESS (sel) 
     VARIABLE A, S, P: STD_LOGIC_VECTOR(16 DOWNTO 0); 
     VARIABLE Ma2: STD_LOGIC_VECTOR(7 DOWNTO 0); 
     --VARIABLE flag: STD_LOGIC; 
    BEGIN 

     IF sel = '0' THEN 
      Ma2 := (NOT oper1) + 1; 
      A := oper1 & "00000000" & '0'; 
      S := Ma2 & "00000000" & '0'; 
      P := "00000000" & oper2 & '0'; 
     ELSE 
      --flag := '0'; 
      FOR i IN 1 TO 8 LOOP 
       IF P(1 DOWNTO 0) = "01" THEN 
        P := P + A; 
        --flag := '0'; 
        --P(17) := flag; 
       ELSIF P(1 DOWNTO 0) = "10" THEN 
        P := P + S; 
        --flag := '1'; 
        --P(17) := flag; 
       END IF; 
       --P(17) := flag; 
       P := P(16) & P(16 downto 1); 
       --P(17) := flag; 
      END LOOP; 
      result <= P(16 DOWNTO 1); 

     END IF; 
    END PROCESS; 
END algor; 

Answer 1

尝试了很多之后，就改变了这一行：P := P(16) & P(16 downto 1);

为这一个：P(16 downto 0) := P(17 downto 1);

而问题解决了！

这里是固定的代码：

LIBRARY IEEE; 
    USE IEEE.STD_LOGIC_1164.ALL; 
    USE IEEE.STD_LOGIC_UNSIGNED.ALL; 

ENTITY algor_booth IS 
    PORT(oper1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); 
     oper2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); 
     sel : IN STD_LOGIC; 
     result : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) 
      ); 
END ENTITY; 

ARCHITECTURE algor OF algor_booth IS 
BEGIN 
    PROCESS (oper1, oper2) 
     VARIABLE A, S, P: STD_LOGIC_VECTOR(17 DOWNTO 0); 
     VARIABLE Ma2: STD_LOGIC_VECTOR(7 DOWNTO 0); 
     VARIABLE flag: STD_LOGIC; 
    BEGIN 
      Ma2 := (NOT oper1) + 1; 
      A := '0' & oper1 & "00000000" & '0'; 
      S := '0' & Ma2 & "00000000" & '0'; 
      P := '0' & "00000000" & oper2 & '0'; 
      flag := '0'; 

      FOR i IN 1 TO 8 LOOP 
       IF (P(1) = '0' AND P(0) = '1') THEN 
        flag := '0'; 
        P(17) := flag; 
          P := P + A; 
       ELSIF (P(1) = '1' AND P(0) = '0') THEN 
        flag := '1'; 
        P(17) := flag; 
          P := P + S; 
       END IF; 
       P(17) := flag; 
       P(16 downto 0) := P(17 downto 1); 
       P(17) := flag; 
      END LOOP; 
      result <= P(16 DOWNTO 1); 
    END PROCESS; 
END algor; 

感谢您的帮助家伙！