这两个vhdl码有什么区别?这2个vhdl码有什么区别
首先:
library IEEE;
use IEEE.Std_Logic_1164.all;
entity mux4 is
port(
in1, in2, in3, in4 : in std_logic;
ctrl: in std_logic_vector(1 downto 0);
sai: out std_logic
);
end mux4;
architecture mux_bhv of mux4 is
begin
process(in1, in2, in3, in4, ctrl)
begin case ctrl is
when "00" => sai <= in1;
when "01" => sai <= in2;
when "10" => sai <= in3;
when "11" => sai <= in4;
when others => null;
end case;
end process;
end mux_bhv;
二:
library IEEE;
use IEEE.Std_Logic_1164.all;
entity mux4x1 is
port(w, x, y, z: in std_logic_vector(7 downto 0);
s: in std_logic_vector(1 downto 0);
m: out std_logic_vector(7 downto 0)
);
end mux4x1;
architecture circuito of mux4x1 is
begin
m <= w when s = "00" else
x when s = "01" else
y when s = "10" else
z;
end circuito;
我的代码没有被构建,所以我将它们上传到了pastebin:http://pastebin.com/mvDVnUNn http://pastebin.com/GQFh9uBZ –
我知道它们都是多路复用器,但是它们之间有区别代码? –
您是否考虑过由综合产生的电路差异,还是模拟差异?一个是'std_logic'与另一个'std_logic_vector(7 downto 0)'之间的多路复用器之间的多路复用器;我认为这不是一个明显的差异,就像你之后... –