如何：多维数组vhdl

Question

我想创建一个VHDL 5维数组，但我不确定如何设置和初始化位。

这里是我到目前为止有：

type \1-line\ is array (4 - 1 downto 0) of unsigned (32 - 1 downto 0); 
    type square is array (4 - 1 downto 0) of \1-line\; 
    type cube is array (4 - 1 downto 0) of square; 
    type hypercube is array (4 - 1 downto 0) of cube; 
    type \5-cube\ is array (4 - 1 downto 0) of cube; 

    signal mega_array : \5-cube\; 
    begin 
     process (clock, reset) begin 
       if (reset == '1') then 
         mega_array <= '0'; 
       end if; 
     end process; 
    end behv; 

Answer 1

一个办法做到这一点是与 '（别人=>' 0 '）'。这是将矢量的所有位设置为'0'的干净安全的方法。您必须为阵列的每一层执行此操作。

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all; 

entity test is 
    port (
     clock : in std_logic; 
     reset : in std_logic); 
end entity test; 

architecture behv of test is 

    type \1-line\ is array (4 - 1 downto 0) of unsigned (32 - 1 downto 0); 
    type square is array (4 - 1 downto 0) of \1-line\; 
    type cube is array (4 - 1 downto 0) of square; 
    type \5-cube\ is array (4 - 1 downto 0) of cube; 

    signal mega_array : \5-cube\; 

begin 

    process (clock, reset) 
    begin 
     if (reset = '1') then   -- note: not '==' 
      mega_array <= (others => (others => (others => (others => (others => '0'))))); 
     end if; 
    end process; 

end architecture behv; 

注意的是，虽然\1-...命名是正确的VHDL，我不会用它来避免讨厌的工具的问题。我不确定他们会来，但避免他们会更好，然后解决它们。我会用t_1line来代替。

Answer 2

聚集是你需要什么：

(others => '0')套在载体中的所有位为“0”

(others => (others => '0'))矢量集的阵列的所有元素的所有位“0”

(others => (others => (others => '0'))) ...等等:)