Systemverilog assertion来检查坏信号转换

Question

我想写一个断言，只有当一个信号在'clk'的上升沿转换时才会触发。我写了下面的代码来测试我的想法

module test(); 

bit clk, clkb; 
int d; 

assign clkb = ~clk; 

initial begin 
    clk = 0; 
    forever #100 clk = ~clk; 
end 

initial begin 
    d = 10; 
    #150 d = 20; 
end 

sva_d_chgd: assert property (@(posedge clk) $stable(d,@(clkb))) 
    else $error($psprintf("err: time = %0d, clk = %b, d = %0d", $time, clk, d)); 

always @ (d or clk) begin 
    $display("time = %0d, clk = %b, d = %0d", $time, clk, d); 
    if ($time > 200) $finish; 
end 
endmodule 

上面的代码返回VCS以下的输出：

time = 0, clk = 0, d = 10 
time = 100, clk = 1, d = 10 
"test.vs", 18: test.sva_d_chgd: started at 100s failed at 100s 
     Offending '$stable(d, @(clkb))' 
Error: "test.vs", 18: test.sva_d_chgd: at time 100 
err: time = 100, clk = 1, d = 10 
time = 150, clk = 1, d = 20 
time = 200, clk = 0, d = 20 
time = 300, clk = 1, d = 20 
$finish called from file "test.vs", line 23. 
$finish at simulation time     300 

为什么在时间100断言火的时候“d”保持稳定，直到时间150？

Answer 1

在你的代码中，在clk的每个posedge上进行稳定检查，以查看“d”的值是否在clkb的前两个边缘之间发生了变化。因为在clk的第一个posedge中没有以前的“d”的clkb边缘值，所以稳定返回“unknown”而不是“true”或“false”，这会导致断言失败。

我已经添加了一个复位信号给你的代码，并禁用断言，直到clk的第一个posedge。当“d”变化时，我也会移动。

module test(); 

bit clk, clkb, rst; 
int d; 

assign clkb = ~clk; 

initial begin 
    clk = 0; 
    forever #100 clk = ~clk; 
end 

initial begin 
    rst = 1; 
    #150 rst = 0; 
end 

initial begin 
    d = 10; 
    #250 d = 20; 
end 

sva_d_chgd: assert property (@(posedge clk) 
          disable iff (rst) 
          $stable(d,@(clkb))) 
    else $error($psprintf("err: time = %0d, clk = %b, d = %0d", $time, clk, d)); 

always @ (d or clk) begin 
    $display("time = %0d, clk = %b, d = %0d", $time, clk, d); 
    if ($time > 400) $finish; 
end 
endmodule 

下面是输出：

# time = 0, clk = 0, d = 10 
# time = 100, clk = 1, d = 10 
# time = 200, clk = 0, d = 10 
# time = 250, clk = 0, d = 20 
# time = 300, clk = 1, d = 20 
# ** Error: err: time = 300, clk = 1, d = 20 
# Time: 300 ns Started: 300 ns Scope: test.sva_d_chgd File: assert_test.sv Line: 26 
# time = 400, clk = 0, d = 20 
# time = 500, clk = 1, d = 20 
# ** Note: $finish : assert_test.sv(30) 
# Time: 500 ns Iteration: 1 Instance: /test 

这得到周围的断言的第一不必要的失败，但我觉得你编码的断言的方式现在还没有真正捕捉你要找的条件。