错误：HDLCompiler：806 ...“end”附近的语法错误

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我是Verilog和FPGA上的新手。所以如果我犯了什么错误，请温和。错误：HDLCompiler：806 ...“end”附近的语法错误

我努力让自己在Verilog内的I2C协议，我打字这家伙打字（一video on YouTube that explains how to make a I2C BUS protocol）

module step1(
input wire clk, 
input wire reset, 
output reg i2c_sda, 
output reg i2c_scl 
); 

//goal is to write to device addres 0x50, 0xaa 

localparam STATE_IDLE = 0; 
localparam STATE_START = 1; 
localparam STATE_ADDR = 2; 
localparam STATE_RW = 3; 
localparam STATE_WACK = 4; 
localparam STATE_DATA = 5; 
localparam STATE_STOP = 6; 
localparam STATE_WACK2 = 7; 
reg [7:0] state; 
reg [6:0] addr; 
reg [7:0] data; 
reg [7:0] count; 

always @(posedge clk) begin 
    if (reset == 1) begin 
     state <= 0; 
     i2c_sda <= 1; 
     i2c_scl <= 1; 
     addr <= 7'h50; 
     count <= 8'd0; 
     data <= 8'haa; 
    end 
    else begin 
     case(state) 

      STATE_IDLE: begin //idle 
       i2c_sda <= 1; 
       state <= STATE_START; 
      end // end state idle 

      STATE_START: begin //start 
       i2c_sda <= 1; 
       state <= STATE_ADDR; 
       count <= 6; 
      end // end of state start 

      STATE_ADDR: begin // fisrt addres bit or the most significant adress bit 
       i2c_sda <= addr[count]; 
       if (count == 0) state <= STATE_RW; 
       else count <= count - 1; 
      end // end of state ADDR 

      STATE_RW: begin // Read or Write opperation 
       i2c_sda <= 1; 
       state <= STATE_WACK; 
      end // end state RW 

      STATE_WACK: begin 
       state <= STATE_DATA; 
       count <= 7; 
      end // end of state WACK 

      STATE_DATA: begin 
       i2c_sda <= data[count]; 
       if (count == 0) state <= STATE_WACK2; 
       else count <= count-1; 
      end // end of state DATA 

      STATE_WACK2: begin 
       state <= STATE_STOP; 
      end // end state WACK2 

      STATE_STOP: begin 
       i2c_sda <= 1; 
       state <= STATE_IDLE; 
      end // end of state STOP 

     end// end of case 
    end // end of the else 
    end // end of if 
endmodule

但是，当我尝试编译下面的错误弹出。我真的不明白，为什么，因为所有的结束都是正确的（至少对我来说）：

ERROR:HDLCompiler:806 - "/home/yunta23/Documentos/Digital1/VideosYou/primero/step1/step1.v" Line 97: Syntax error near "end".

关于此错误的任何解释将帮助我在我的决赛！非常感谢你。

来源

2014-12-07 Julian Marín

你的错误说，它是在97号线有80只在您发布的代码行。这使我们更难确定编译器认为错误在哪里。请参阅[如何创建最小，完整和可验证示例]（http://stackoverflow.com/help/mcve）。生成[MCVE]（http://stackoverflow.com/help/mcve）可能会导致您自行找到错误。 – Makyen 2014-12-07 03:46:09

A case声明需要endcase关键字，而不是end关键字。变化：

end// end of case

到：

endcase

来源

2014-12-07 03:14:17 toolic

你是对的，我的回答是在黑暗中拍摄的，你的答案可能是正确的。我删除了我的个人资料，以免分散注意力 – Sentry 2014-12-07 16:42:37

错误：HDLCompiler：806 ...“end”附近的语法错误

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