错误：HDLCompiler：806部分被忽略的语法错误为什么会被忽略？

Question

我需要写这个状态机控制FIFO数据路径，但似乎在其他地方被忽略语法错误，不要让我完成正常的状态机。

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 

entity FIFO_FSM is 
    Port (CMD_WR_H : in STD_LOGIC; 
      CMD_RD_H : in STD_LOGIC; 
      SYS_CLK_H : in STD_LOGIC; 
      RST_H : in STD_LOGIC; 
      EMPTY_H : out STD_LOGIC; 
      FULL_H : out STD_LOGIC; 
      LD_EN_0_H : out STD_LOGIC; 
      LD_EN_1_H : out STD_LOGIC; 
      LD_EN_2_H : out STD_LOGIC; 
      LD_EN_3_H : out STD_LOGIC; 
      RD_EN_H : out STD_LOGIC; 
      WR_EN_H : out STD_LOGIC; 
      LD_RVR_H : out STD_LOGIC); 
end FIFO_FSM; 

architecture Behavioral of FIFO_FSM is 
signal PresentState,Nextstate: integer := 0; 
begin 

process(PresentState,CMD_WR_H,CMD_RD_H,RST_H) 
begin 

case PresentState is 

when 0 => -- empty state 
LD_EN_0_H <='0';LD_EN_1_H <='0';LD_EN_2_H <='0';LD_EN_3_H <='0'; 
RD_EN_H<='0';WR_EN_H<='0';LD_RVR_H<='0'; 
EMPTY_H<='1';FULL_H<='0'; 
if(RST_H ='1') then Nextstate<=0; 
elsif(((CMD_WR_H ='1' and CMD_RD_H='1') and (RST_H='0'))) then Nextstate<=0; 
elsif((((CMD_WR_H='0') and (CMD_RD_H='0')) and (RST_H='0')))then Nextstate<=0; 
elsif(((CMD_WR_H='0' and (CMD_RD_H='1')) and (RST_H='0')))then Nextstate<=0; 
elsif((((CMD_WR_H='1') and CMD_RD_H='0') and (RST_H='0')))then Nextstate<=1; 
end if; 

when 1 => --loading Reg 0 transition state 
LD_EN_0_H <='1';LD_EN_1_H <='0';LD_EN_2_H <='0';LD_EN_3_H <='0'; 
RD_EN_H<='0';WR_EN_H<='1';LD_RVR_H<='0'; 
EMPTY_H<='0';FULL_H<='0'; 
Nextstate<=2; 


when 20=> -- unloading R0 
LD_EN_0_H <='1';LD_EN_1_H <='1';LD_EN_2_H <='1';LD_EN_3_H <='1'; 
RD_EN_H<='1';WR_EN_H<='0';LD_RVR_H<='1'; 
EMPTY_H<='0';FULL_H<='0'; 
Nextstate<=0; 

when 2=> -- Reg 0 stored 
LD_EN_0_H <='0';LD_EN_1_H <='0';LD_EN_2_H <='0';LD_EN_3_H <='0'; 
RD_EN_H<='0';WR_EN_H<='0';LD_RVR_H<='0'; 
EMPTY_H<='0';FULL_H<='0'; 
if(RST_H ='1') then Nextstate<=0; 
elsif(((CMD_WR_H ='1' and CMD_RD_H='1') and (RST_H='0'))) then Nextstate<=2; 
elsif((((CMD_WR_H='0') and (CMD_RD_H='0')) and (RST_H='0')))then Nextstate<=2; 
elsif(((CMD_WR_H='0' and (CMD_RD_H='1')) and (RST_H='0')))then Nextstate<=20; 
elsif((((CMD_WR_H='1') and CMD_RD_H='0') and (RST_H='0')))then Nextstate<=3; 
end if; 

when 3=> --Load Reg 1 transition state 
LD_EN_0_H <='0';LD_EN_1_H <='1';LD_EN_2_H <='0';LD_EN_3_H <='0'; 
RD_EN_H<='0';WR_EN_H<='1';LD_RVR_H<='0'; 
EMPTY_H<='0';FULL_H<='0'; 
Nextstate<=4; 

when 42 => --unloading R1 
LD_EN_0_H <='1';LD_EN_1_H <='1';LD_EN_2_H <='1';LD_EN_3_H <='1'; 
RD_EN_H<='1';WR_EN_H<='0';LD_RVR_H<='1'; 
EMPTY_H<='0';FULL_H<='0'; 
Nextstate<=2; 


when 4=> --Reg 1 Stored 
LD_EN_0_H <='0';LD_EN_1_H <='0';LD_EN_2_H <='0';LD_EN_3_H <='0'; 
RD_EN_H<='0';WR_EN_H<='0';LD_RVR_H<='0'; 
EMPTY_H<='0';FULL_H<='0'; 
if(RST_H ='1') then Nextstate<=0; 
elsif(((CMD_WR_H ='1' and CMD_RD_H='1') and (RST_H='0'))) then Nextstate<=4; 
elsif((((CMD_WR_H='0') and (CMD_RD_H='0')) and (RST_H='0')))then Nextstate<=4; 
elsif(((CMD_WR_H='0' and (CMD_RD_H='1')) and (RST_H='0')))then Nextstate<=42; 
elsif((((CMD_WR_H='1') and CMD_RD_H='0') and (RST_H='0')))then Nextstate<=5; 
end if; 

when 5=> --Load Reg 2 transition state 
LD_EN_0_H <='0';LD_EN_1_H <='0';LD_EN_2_H <='1';LD_EN_3_H <='0'; 
RD_EN_H<='0';WR_EN_H<='1';LD_RVR_H<='0'; 
EMPTY_H<='0';FULL_H<='0'; 
Nextstate<=6; 

when 64 -- unloading R2 
LD_EN_0_H <='1';LD_EN_1_H <='1';LD_EN_2_H <='1';LD_EN_3_H <='1'; 
RD_EN_H<='1';WR_EN_H<='0';LD_RVR_H<='1'; 
EMPTY_H<='0';FULL_H<='0'; 
Nextstate<=4; 

when 6=> -- Reg 2 Stored 
LD_EN_0_H <='0';LD_EN_1_H <='0';LD_EN_2_H <='0';LD_EN_3_H <='0'; 
RD_EN_H<='0';WR_EN_H<='0';LD_RVR_H<='0'; 
EMPTY_H<='0';FULL_H<='0'; 
if(RST_H ='1') then Nextstate<=0; 
elsif(((CMD_WR_H ='1' and CMD_RD_H='1') and (RST_H='0'))) then Nextstate<=6; 
elsif((((CMD_WR_H='0') and (CMD_RD_H='0')) and (RST_H='0')))then Nextstate<=6; 
elsif(((CMD_WR_H='0' and (CMD_RD_H='1')) and (RST_H='0')))then Nextstate<=64; 
elsif((((CMD_WR_H='1') and CMD_RD_H='0') and (RST_H='0')))then Nextstate<=7; 
end if; 

when 7=> -- Load Reg 3 transition state 
LD_EN_0_H <='0';LD_EN_1_H <='0';LD_EN_2_H <='0';LD_EN_3_H <='1'; 
RD_EN_H<='0';WR_EN_H<='1';LD_RVR_H<='0'; 
EMPTY_H<='0';FULL_H<='0'; 
Nextstate<=8; 

when 86 -- unloading R3 
LD_EN_0_H <='1';LD_EN_1_H <='1';LD_EN_2_H <='1';LD_EN_3_H <='1'; 
RD_EN_H<='1';WR_EN_H<='0';LD_RVR_H<='1'; 
EMPTY_H<='0';FULL_H<='0'; 
Nextstate<=6; 

when 8=> -- Reg 3 Stored 
LD_EN_0_H <='0';LD_EN_1_H <='0';LD_EN_2_H <='0';LD_EN_3_H <='0'; 
RD_EN_H<='0';WR_EN_H<='0';LD_RVR_H<='0'; 
EMPTY_H<='0';FULL_H<='1'; 
if(RST_H ='1') then Nextstate<=0; 
elsif(((CMD_WR_H ='1' and CMD_RD_H='1') and (RST_H='0'))) then Nextstate<=8; 
elsif((((CMD_WR_H='0') and (CMD_RD_H='0')) and (RST_H='0')))then Nextstate<=8; 
elsif(((CMD_WR_H='0' and (CMD_RD_H='1')) and (RST_H='0')))then Nextstate<=86; 
elsif((((CMD_WR_H='1') and CMD_RD_H='0') and (RST_H='0')))then Nextstate<=8; 
end if; 

end process; 

process(CLK)       -- State Register 
    begin 
     if CLK='1' and CLK'EVENT then  -- rising edge of clock 
     PresentState <= Nextstate; 
    end if; 
    end process; 

end Behavioral; 

我得到这些错误：

ERROR:HDLCompiler:806 - "C:/Users/willow/workspaceVHDL/FSM/FIFO_FSM.vhd" Line 96: Syntax error near "<=". 
ERROR:HDLCompiler:806 - "C:/Users/willow/workspaceVHDL/FSM/FIFO_FSM.vhd" Line 119: Syntax error near "<=". 
ERROR:HDLCompiler:806 - "C:/Users/willow/workspaceVHDL/FSM/FIFO_FSM.vhd" Line 135: Syntax error near "process". 

我想要问的是什么错误，以及如何解决它，因为是说像我不能使用<=来分配对我的投入和产出有价值，但仅限于某些方面，而不是其他方面。我得到的另一个错误是在对时钟敏感的进程之前的最后进程线附近。

Answer 1

首先，你应该格式化你的代码，使其可读：

• 缩进你的代码相匹配的逻辑层次
• 在同一行，避免多任务操作员
之间
• 使用空格

您的代码可能对你有意义了，但是当你回来这个代码在几个月，或者别人必须与它的工作，良好的格式化代码无线的好处会很快变得明显。

你的第一和第二错误是因为你有例如when 64，忘记=>。应该说，例如when 64 =>。

第三个错误是因为您有case声明，没有匹配end case。你的说法应该是这个样子：

case PresentState is 
    when 0 => 
    -- do something 
    when 1 => 
    -- do something else 
end case; 

这里的最后一行是你错过了什么。

已经解决了case语句的问题，接下来的问题是，您的代码使用CLK，这不是输入到你的实体。

接下来的问题是，你的case语句没有覆盖所有可能的情况。您可以通过在case语句的末尾添加一个最终when others =>情况下，或通过使用一个枚举类型的case语句解决这个问题。枚举类型将是我的选择，以保持可读性：

type STATE_MACHINE_type is (IDLE, LOAD_DATA, RESET); 
signal PresentState : STATE_MACHINE_type := IDLE; 

...

case PresentState is 
    when IDLE => 
    Nextstate <= LOAD_DATA; 
    when LOAD_DATA => 
    Nextstate <= RESET; 
    when RESET => 
    Nextstate <= IDLE; 
end case; 

如果你决定使用when others =>方法，但没有代码，把在这种情况下，你可以使这个明确使用NULL：

case PresentState is 
    when 0 => 
    -- do something 
    when others => 
    NULL; 
end case;