2015-02-18 35 views
0

你好,我想完成这件事VHDL-交换机正确的代码

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,我已经写了这个代码,是正确的吗? 因为我在MAX + PLUS II编译器不显示任何错误...

LIBRARY IEEE; 
USE IEE.STD_LOGIC_1164.ALL; 

ENTITY alarm IS PORT 
(ON/OFF,MOTION_SENSOR,.LIGHT_SENSOR,.SOUND_SENSOR,.CAMERA_SENSOR,.IP_SENSOR,.TEMPERATURE_SENSOR: IN STD_LOGIC; 
SENSOR_SIRINE,SENSOR_LIGHT:OUT STD_LOGIC); 
END alarm; 

ARCHITECTURE LEITOURGEIA OF alarm IS 
BEGIN 
if (ON/OFF='1' AND (MOTION_SENSOR='1' OR LIGHT_SENSOR='1' OR SOUND_SENSOR='1' OR CAMERA_SENSOR='1' OR IP_SENSOR='1' OR TEMPERATURE_SENSOR='1')) then 
SENSOR_LIGHT<='1'; 
SENSOR_SIRINE<='1'; 

ELSE IF (ON/OFF='0' AND (MOTION_SENSOR='1' OR LIGHT_SENSOR='1' OR SOUND_SENSOR='1' OR CAMERA_SENSOR='1' OR IP_SENSOR='1' OR TEMPERATURE_SENSOR='1')) then 
SENSOR_LIGHT<='1'; 
SENSOR_SIRINE<='0'; 

ELSE 
SENSOR_LIGHT<='0'; 
SENSOR_SIRINE<='0'; 

END IF 

END LEITOURGEIA; 
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你错过了一个分号:

而这其中甚至更类似于参考电路。 ON/OFF不是VHDL中的合法标识符,也不是以句点开头的标识符。 if语句不是并发语句。 – user1155120 2015-02-18 00:17:30

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不是合法标识符的含义?开/关是输入 – 2015-02-18 00:19:09

+2

伙计,这不是VHDL。 – user1155120 2015-02-18 00:21:51

回答

1

这是你的代码是什么样子的有效VHDL近似:

library ieee; 
use ieee.std_logic_1164.all; 

entity alarm is 
    port (
     on_off, motion_sensor, light_sensor, 
     sound_sensor, camera_sensor, ip_sensor, 
     temperature_sensor:   in std_logic; 
     sensor_sirine, sensor_light: out std_logic 
    ); 
end alarm; 

architecture leitourgeia of alarm is 
begin 
unlabelled: 
    process (on_off, motion_sensor, light_sensor, sound_sensor, 
      camera_sensor, ip_sensor, temperature_sensor) 
    begin 
     if on_off = '1' and 
      (motion_sensor = '1' or light_sensor = '1' or sound_sensor = '1' or 
      camera_sensor = '1' or ip_sensor = '1' or temperature_sensor='1') then 
      sensor_light <= '1'; 
      sensor_sirine <= '1'; 
     elsif on_off = '0' and 
      (motion_sensor = '1' or light_sensor = '1' or sound_sensor = '1' or 
      camera_sensor = '1' or ip_sensor = '1' or temperature_sensor = '1') then 
      sensor_light <= '1'; 
      sensor_sirine <= '0'; 
     else 
      sensor_light <= '0'; 
      sensor_sirine <= '0'; 
     end if; 
    end process; 
end leitourgeia; 

我缩进它,固定一些拼写错误,使有效的标识符,把if语句放在一个进程中,并使elsifelsif,加上摆脱两组多余的括号。

它现在分析,阐述和模拟。

所以做这种架构:

architecture foo of alarm is 
    signal alarm_light: std_logic; 
begin 
    alarm_light <= motion_sensor or sound_sensor or light_sensor or 
        camera_sensor or ip_sensor or temperature_sensor; 

    sensor_light <= alarm_light; 

    sensor_sirine <= '1' when alarm_light = '1' and on_off = '1' else 
        '0'; 
end architecture foo; 

哪个更类似于参考电路图像。在`结束后if`

architecture fum of alarm is 
    signal alarm_light: std_logic; 
begin 
    alarm_light <= motion_sensor or sound_sensor or light_sensor or 
        camera_sensor or ip_sensor or temperature_sensor; 

    sensor_light <= alarm_light; 

    sensor_sirine <= on_off and alarm_light; 
end architecture fum; 
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非常感谢 – 2015-02-18 00:40:57

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以大写形式输入,输出和语句(if,elseif)的名称是否存在问题? – 2015-02-18 00:42:29

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不,这不是问题,常规标识符和保留字不区分大小写; – user1155120 2015-02-18 00:43:36