当MCR或MRC指令执行与不同CRM或OPT2，那么什么是CRN寄存器的状态？ 例如，如果运行：系统控制寄存器中的ARM Cortex-A7
asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r"(val))
或
asm volatile("mcr p15, 0, %0, c9, c13, 2" : : "r"(val))
然后，该寄存器的值将被改变C9或C13？以及最后一个选项（0或2）的作用是什么？ here
MCR和MRC指令是通用协处理器指令。什么这些指令做取决于你使用特定的硬件，有什么样的协处理器，以及操作码和协处理器寄存器操作数的值（opcode1，opcode2，CRn的和CRm上）。协处理器寄存器操作数不一定指实际的协处理器寄存器，因此实际上是附加的操作码操作数。
要了解MCR/MRC阻塞的功能，您需要在硬件特定的文档中查找此代码要运行的特定CPU。因此，在您的示例中，我们需要查看Cortex-A7's documentation for coprocessor 15，这是系统控制“协处理器”。此页面列出了可以在使用这些说明CRn的，opcode1，CRm上访问的系统控制寄存器，opcode2秩序。
在这两个你的例子CRn的是C9，并寻找，最多的文档中导致我们a page describing mostly performance monitoring related registers。在您的第一个示例中，操作码1为0,CRm为13,操作码2为0，该页告诉我们该指令写入PMCR或性能监视器控制寄存器。对于第二个示例，操作码1为0,CRm为13,操作码2为2，表示它访问PMNCNTENCLR或计数使能清除寄存器。
你最好认为op1，op2，crn和crm构成了某个寄存器地址。后者指令将协处理器15寄存器0，c9，c13,2（PMXEVCNTR，性能监视器事件计数寄存器）设置为包含在C编译器决定用于变量'val'的寄存器中的值。
对于除性能计数器寄存器其他：由协处理器寄存器号码 图B3-26 B3.17.1 CP15寄存器总结概括了由主协处理器寄存器编号CP15寄存器用于VMSAv7 执行分组。
CRn opc1 CRm opc2
c0 {0-2} {c0-c7} {0-7} ¶ ID registers
c1 {0, 4} {c0, c1} {0-7} System control registers
c2 {0, 4} {c0, c1} {0-2} Memory protection and
c3 0 c0 0 control registers
c5 {0, 4} {c0,c1} {0,1} Memory system
c6 {0, 4} c0 {0, 2, 4} fault registers
c7 {0, 4} Various Various ¶ Cache maintenance, address translations, miscellaneous
c8 {0, 4} Various Various TLB maintenance operations
c9 {0-7} Various {0-7} ¶ Reserved for performance monitors and maintenance operations
c10 {0-7} Various {0-7} ¶ Memory mapping registers and TLB operations
c11 {0-7} {c0-c8,c15} {0-7} ¶ Reserved for DMA operations for TCM access
c12 {0, 4} {c0,c1} {0,1} ¶ Security Extensions registers, if implemented
c13 {0, 4} c0 {0-4} ¶ Process, context, and thread ID registers
c14 {0-7} {c0-c15} {0-7} ¶ Generic Timer registers, if implemented
c15 {0-7} {c0-c15} {0-7} ¶ IMPLEMENTATION DEFINED registers
Read-only Read/Write Write-only ¶ Access depends on the implementation
Figure B3-26 CP15 register grouping by primary coprocessor register, CRn, VMSA implementation
关于调试寄存器，有一个描述： C6.4。1使用CP14访问调试寄存器 访问在CP14接口中可见的寄存器通常使用以下协处理器指令： •用于读取访问的MRC。 •用于写入访问的MCR。
In addition, the following coprocessors instructions are defined for specific registers accesses:
MRRC Read access to the Debug ROM Address Register, DBGDRAR, and the Debug Self Address Offset
Register, DBGDSAR, in an implementation that includes the Large Physical Address Extension.
STC Read access to the Host to Target Data Transfer Register, DBGDTRRXint.
LDC Write access to the Target to Host Data Transfer Register, DBGDTRTXint.
Form of MRC and MCR instructions
The form of the MRC and MCR instructions used for accessing debug registers through the CP14 interface is:
MRC p14, 0, <Rt>, <CRn>, <CRm>, <opc2> ; Read
MCR p14, 0, <Rt>, <CRn>, <CRm>, <opc2> ; Write
Where <Rt> refers to any of the ARM core registers R0-R14. Use of R13 is UNPREDICTABLE in Thumb and
ThumbEE states, and is deprecated in ARM state. <CRn>, <CRm>, and <opc2> are mapped from the debug register
number as shown in Figure C6-1
The use of the MRC APSR_nzcv form of the MRC instruction is permitted for reads of the DBGDSCRint only. Use with
other registers is UNPREDICTABLE. See CP14 interface 32-bit access instructions, required in all versions of the
Debug architecture on page C6-2124 for more information.
For accesses to the debug registers, <CRn> <= 0b0111 and therefore bit[10] of the value in the figure is 0.
10 9 8 7 6 5 4 3 2 1 0
Value 0 Register number[9:0]
Arguments CRn[3:0] opc2[2:0] CRm[3:0]
Figure C6-1 Mapping from debug register number to CP14 instruction arguments
打我稍微。 :-) – turboscrew
所以，我们可以说，没有什么像寄存器cRn，cRm这些只是PMCR或计数使能清除寄存器等内核地址。对？ 并且为了访问这些寄存器，我们需要指令（mcr/mrc），根据hw的具体文档。 – enfinet
@enfinet基本上，除ARM寄存器操作数以外的每个操作数都是需要在表中查找以便查找了解指令的功能。 –