VHDL - 设计库不包含单位

Question

我有以下结构：上线Error (10481): VHDL Use Clause error at DE2_TOP.vhd(276): design library "work" does not contain primary unit "lab1"：

architecture datapath of DE2_TOP is 
begin 
U1: entity work.lab1 port map (
    clock => clock_50, 
    key => key, 
    hex6 => hex6, 
    hex5 => hex5, 
    hex4 => hex4 
); 
end datapath; 

我收到以下错误U1: entity work.lab1 port map (。任何人都知道是什么导

Answer 1

您需要编译至少entity为lab1编译DE2_TOP