不必要的一个时钟延迟vhdl

Question

有人可以解释我为什么我有一个时钟延迟对我的模拟以下，我该如何解决它，它不应该在那里，因为我在输出上丢失了一点....

entity outBit is 
port( clk1 : in STD_LOGIC; 
     clk2 : in STD_LOGIC; 
     -- reset : in STD_LOGIC; 
     int_in : in INTEGER; 
     bit_out : out STD_LOGIC); --_VECTOR of 32 
end outBit ; 

是我的实体和每个上升沿clk 1它需要一个整数。根据它是什么整数（1,2,3,4 ...），它选择一个数组的相应行。该行是32位的。我想输出32位中的一位clk2。例如，如果clk1 = 100然后clk2 = 100/32。

architecture Behavioral of outBit is 
signal temp : array; --the array is fixed 
signal output_bits : std_logic_vector(31 downto 0); 
signal bit_i : integer := 31; --outputting a single bit out of 32 each time 
begin 

    temp(0) <= "11111111111111111111111111111111"; 
    temp(1) <= "11111111111111111111111111111110"; 
    temp(2) <= "11111111111111111111111111111100"; 
    -- etc 

output_bits <= temp(int_in); 

    process(clk2) 
     --outputting a single bit out of 32 each time 
     --variable bit_i : integer := 31; 
     begin 
     if rising_edge(clk2) then 
      bit_out <= output_bits(bit_i); 
      if bit_i = 0 then 
      bit_i <= 31; 
      else 
      bit_i <= bit_i - 1; 
      end if; 
     end if; 
     end process; 
end Behavioral; 

不需要的延迟如下所示。我想每32个周期来读取新行（根据输入整数）等....

顺便firstclock（在代码中），（在图片第二时钟）是不是真的相对于问题的目的只是为了让想法时，整数即将

Answer 1

如果你想摆脱bit_out延迟不让它触发器：

library ieee;      -- add missing context clause 
use ieee.std_logic_1164.all; 

entity outbit is 
    port (
    -- clk1:  in std_logic; -- not relevant 
     clk2:  in std_logic; 
    -- reset:  in std_logic; 
     int_in:  in integer; 
     bit_out: out std_logic --_vector of 32 
    ); 
end entity outbit; 

architecture behavioral of outbit is 
    type bit_array is array (0 to 3) of std_logic_vector(0 to 31); -- added 
    signal temp : bit_array; --the array is fixed -- non_reserved word name 
    signal output_bits : std_logic_vector(31 downto 0); 
    subtype index_int is integer range 0 to 31; -- changed bit_i type 
    signal bit_i: index_int := 31; --outputting a single bit out of 32 each time 

begin 

    temp(0) <= "11111111111111111111111111111111"; 
    temp(1) <= "11111111111111111111111111111110"; 
    temp(2) <= "11111111111111111111111111111100"; 
    temp(3) <= "11011001110000110101001000101110"; -- added 
    -- etc 

    output_bits <= temp(int_in); 

    process(clk2) 
     --outputting a single bit out of 32 each time 
     --variable bit_i : integer := 31; 
     begin 
     if rising_edge(clk2) then 
     -- bit_out <= output_bits(bit_i); -- moved 
      if bit_i = 0 then 
      bit_i <= 31; 
      else 
      bit_i <= bit_i - 1; 
      end if; 
     end if; 
     end process; 

     bit_out <= output_bits(bit_i);   -- moved to here 

end architecture behavioral; 

移动在statem以外的时钟之外的bit_out分配ENT。 （它可以是并发信号分配，代表32：1多路复用器）。

添加一个测试台完成Minimal, Complete, and Verifiable example：

library ieee; 
use ieee.std_logic_1164.all; 

entity outbit_tb is 
end entity; 

architecture foo of outbit_tb is 
    signal clk2: std_logic := '1'; 
    subtype temp_index is integer range 0 to 3; 
    signal int_in: temp_index := 3; 
    signal bit_out: std_logic; 
begin 
CLOCK: 
    process 
    begin 
     wait for 5 ns; -- so can multiply clocks in my head to get stop time 
     clk2 <= not clk2; 
     if now > 360 ns then 
      wait; 
     end if; 
    end process; 
DUT: 
    entity work.outbit 
     port map (
      clk2 => clk2, 
      int_in => int_in, 
      bit_out => bit_out 
     ); 
end architecture; 

和延迟消失：