VHDL错误错误（10822）：无法实现赋值寄存器

Question

我尝试实现具有异步预设和清除功能的JK触发器，并在时钟上具有正边沿逻辑。

我收到以下错误Altera提供的Quartus II：

Error (10822): HDL error at JK_FF_PE_D1.vhd(52): couldn't implement registers for assignments on this clock edge

Error: Can't elaborate top-level user hierarchy

我没有看到错误......我将成为一个尖头或忠告，真的很感谢。

预先感谢您！

library ieee; 
use ieee.std_logic_1164.all; 

entity JK_FF_PE_D1 is 
    port(
    J, K  : in std_logic; -- J, K inputs of flip flop 
    PS   : in std_logic; -- Preset of flip flop 
    CLR   : in std_logic; -- CLR of flip flop 
    CLK   : in std_logic; -- Clock 
    Q, Qcompl : out std_logic -- Q and its complementary output 
    ); 
end entity JK_FF_PE_D1; 

architecture simple of JK_FF_PE_D1 is 
    signal temp_Q, temp_Qcompl : std_logic; 

begin 

    p0:process(PS, CLR, CLK) is 
    begin 
    case std_logic_vector'(PS, CLR) is 
      when "00" => 
      temp_Q <= '1'; 
      temp_Qcompl <= '1'; 
      when "01" => 
      temp_Q <= '1'; 
      temp_Qcompl <= '0'; 
      when "10" => 
      temp_Q <= '0'; 
      temp_Qcompl <= '1'; 
      when others => -- Preset = 1 , Clear = 1 
      if rising_edge (CLK) then -- Clock turns from 0 -> 1 
       case std_logic_vector'(J, K) is 
        when "11" => 
         temp_Q <= not temp_Q; 
         temp_Qcompl <= not temp_Qcompl; 
        when "10" => 
         temp_Q <= '1'; 
         temp_Qcompl <= '0'; 
        when "01" => 
         temp_Q <= '0'; 
         temp_Qcompl <= '1'; 
        when others => 
         null; 
       end case; 
      end if; 
    end case; 
    end process p0; 
    Q <= temp_Q; 
    Qcompl <= not temp_Qcompl; 

end architecture simple; 

Answer 1

它看起来像在Altera公司的Quartus II的限制，由于如下所示的外case可以被改变为if，然后它可以通过合成运行：

p0 : process(ps, CLR, CLK) is 
begin 
    if std_logic_vector'(ps, CLR) = "00" then 
    temp_Q  <= '1'; 
    temp_Qcompl <= '1'; 
    elsif std_logic_vector'(ps, CLR) = "01" then 
    temp_Q  <= '1'; 
    temp_Qcompl <= '0'; 
    elsif std_logic_vector'(ps, CLR) = "10" then 
    temp_Q  <= '0'; 
    temp_Qcompl <= '1'; 
    else        -- Preset = 1 , Clear = 1 
    if rising_edge (CLK) then  -- Clock turns from 0 -> 1 
     case std_logic_vector'(J, K) is 
     when "11" => 
      temp_Q  <= not temp_Q; 
      temp_Qcompl <= not temp_Qcompl; 
     when "10" => 
      temp_Q  <= '1'; 
      temp_Qcompl <= '0'; 
     when "01" => 
      temp_Q  <= '0'; 
      temp_Qcompl <= '1'; 
     when others => 
      null; 
     end case; 
    end if; 
    end if; 
end process p0; 

如果特定的目标设备不允许异步设置和复位的触发器，则发出警告。