我在使用这段代码时遇到了一些麻烦。看起来状态S0总是有效的,即使它不应该是。看起来这个状态的输出是反转的(当它被禁止时是有效的)。有任何想法吗?底部的模拟打印。由于VHDL为什么当状态S0不应该是活动状态?
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity ControlUnit is
port(clk : in std_logic;
reset : in std_logic;
validTime : in std_logic;
timeData : in std_logic_vector(3 downto 0);
writeEnable : out std_logic;
writeAddress : out std_logic_vector(3 downto 0);
averageReady : out std_logic);
end ControlUnit;
architecture Behavioral of ControlUnit is
type TState is (S0, S1, S2, S3, S4, S5);
signal PState, NState: TState;
begin
sync_proc: process(clk, reset)
begin
if(reset = '1') then
PState <= S0;
elsif(rising_edge(clk)) then
PState <= NState;
end if;
end process;
comb_proc: process(PState, validTime, timeData)
begin
averageReady <= '0';
writeEnable <= '0';
case PState is
when S0 =>
if(validTime = '1') then
writeEnable <= '1';
NState <= S1;
else
NState <= S0;
end if;
when S1 =>
if(validTime = '1') then
writeEnable <= '1';
NState <= S2;
else
NState <= S1;
end if;
when S2 =>
if(validTime = '1') then
writeEnable <= '1';
NState <= S3;
else
NState <= S2;
end if;
when S3 =>
if(validTime = '1') then
writeEnable <= '1';
NState <= S4;
else
NState <= S3;
end if;
when S4 =>
if(validTime = '1') then
writeEnable <= '1';
NState <= S5;
else
NState <= S4;
end if;
when S5 =>
averageReady <= '1';
NState <= S0;
when others =>
NState <= S0;
end case;
end process;
with PState select
writeAddress <= "0000" when S0,
"0001" When S1,
"0010" when S2,
"0011" when S3,
"0100" when S4,
"XXXX" when others;
end Behavioral;
这里是模拟的打印:
这似乎是一个热门编码(暗示这是后合成模拟)。 PState.S0的极性看起来是倒置的,而其余的看起来是正确的。合成的硬件需要保持极性直线,但PState不是输出,它是否正确模拟?您尚未提供允许预综合模拟的[最小,完整和可验证示例](http://stackoverflow.com/help/mcve)。 *任何想法?*对于一个问题有点宽泛。如果你想要在内部进行同步,也许你可以以不同的方式限制合成。 – user1155120