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我想实现一个D触发器在VHDL中,使用我写的D锁存器。 但时钟似乎有错误,我无法弄清楚是什么。D触发器在VHDL
这是我的D锁存器的代码。
Library ieee;
Use ieee.std_logic_1164.all;
entity d_latch is
port (c,d : in std_logic;
q,nq : out std_logic);
end d_latch;
architecture arch of d_latch is
Signal qt, nqt: std_logic;
begin
qt <= (d nand c) nand nqt;
nqt <= ((not d) nand c) nand qt;
q <= qt;
nq <= nqt;
end arch;
我测试了它和它的作品,这里是我的d触发器代码:
Library ieee;
Use ieee.std_logic_1164.all;
entity d_flipflop is
port (d,clock : in std_logic;
q,nq : out std_logic);
end d_flipflop;
architecture arch of d_flipflop is
Component d_latch
Port
(
d, clk: in std_logic;
q, nq : out std_logic
);
End Component ;
Signal qt, nqt: std_logic;
begin
dl1: d_latch port map (
d => d,
clk => not clock,
q => qt
);
dl2: d_latch port map (
d => qt,
clk => clock,
q => q,
nq => nq
);
end arch;
,这里是错误:
** Error: /home/devplayer/CSC343/Lab_2_Content/d_flipflop.vhd(25): (vcom-1436) Use of non globally static actual (prefix expression) of formal "clk" requires VHDL 2008.
谢谢
明白了,谢谢! – ratsimihah 2012-02-15 03:30:34