0
我正在写一个进程,必须寻找每一个传入位,跟踪接收或不接收的总数是1,并且,当时间到了必须比较该值为参考值。该过程如下:信号下降到未定义,而所有相关的信号被定义
parity_tester : process(clk, sub_rst, barrel_data_in, barrel_enable, parity_test, parity_ref)
variable last_known_enable : boolean := false;
variable last_known_data : STD_LOGIC := '0';
variable parity_error_out : STD_LOGIC := '0';
variable parity_ref_reg : STD_LOGIC := '0';
variable even : STD_LOGIC := '1';
begin
if sub_rst then
last_known_enable := false;
last_known_data := '0';
parity_error_out := '0';
even := '1';
elsif rising_edge(clk) then
if barrel_enable then
last_known_enable := true;
last_known_data := barrel_data_in;
else
if last_known_enable then
last_known_enable := false;
if last_known_data = '1' then
even := not even;
end if;
end if;
end if;
if parity_test then
case parity_bit_in_type is
when 0 =>
parity_error_out := even xnor parity_ref;
when 1 =>
parity_error_out := even xor parity_ref;
when 2 =>
parity_error_out := parity_ref;
when 3 =>
parity_error_out := not parity_ref;
when others =>
parity_error_out := '1';
end case;
end if;
end if;
parity_error <= parity_error_out;
end process;
在这里,我遇到一个问题:由于在这个过程中灵敏度列表中定义的所有信号被定义,但根据GHDL(模拟器)的值变为不确定的每当parity_test变为真: 我在做什么错?
我删除了这里因为当我改变到我的笔记本电脑,错误改变了:它关于案件开关。我仍然不明白为什么。 parity_bit_in_type是一个范围(0到3)的通用Natural。如果我拿出我需要的语句(在这种情况下为0)并删除案例,所有事情都按预期工作。 WebPack ISE似乎没有抱怨,所以它开始感觉像GHDL中的错误。
GHDL版本:
/Downloads/ghdl-gcc-git » ghdl --version
GHDL 0.34dev (20151126) [Dunoon edition]
Compiled with GNAT Version: 5.3.0
mcode code generator
Written by Tristan Gingold.
Copyright (C) 2003 - 2015 Tristan Gingold.
GHDL is free software, covered by the GNU General Public License. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
一个最小的例子显示了相同的行为
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity uart_receiv_parity is
generic (
parity_bit_in_type : Natural range 0 to 3
);
port (
rst : in boolean;
clk : in STD_LOGIC;
parity_error : out STD_LOGIC -- Signals that the parity check has failed, is zero if there was none
);
end entity;
architecture Behavioral of uart_receiv_parity is
begin
parity_tester : process(clk, rst)
variable parity_error_out : STD_LOGIC := '0';
begin
if rst then
parity_error_out := '0';
elsif rising_edge(clk) then
case parity_bit_in_type is
when 0 =>
parity_error_out := '1';
when 1 =>
parity_error_out := '0';
when 2 =>
parity_error_out := '1';
when 3 =>
parity_error_out := '0';
when others =>
parity_error_out := '1';
end case;
end if;
parity_error <= parity_error_out;
end process;
end Behavioral;
不,我不知道。另一个好奇的是,如果我更改为parity_error_out:= even,那么这个未定义的事情就不会再发生了。 – Cheiron
什么是GHDL版本和后端?红色区域依赖于输入数据的时间是多少?红色值是'U'还是'X'? – Paebbels
将进程置于新体系结构中并对其应用刺激时,错误仍然会发生吗? –