ALU +移位寄存器

我必须制作一个连接到移位寄存器的8位ALU。我认为这是ALU的代码，但连接它的最佳方式是什么？8位移位寄存器与复位和时钟？林不知道如何使用内部信号，这两个组件连接，他们都应该有独立的ALU +移位寄存器

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL;    -- Calling libary's to be used 
use IEEE.NUMERIC_STD.ALL; 

entity lu is 
port( Clk : in std_logic;    -- The clock signal 
     A : in signed(7 downto 0);   -- The A Input 
     B : in signed(7 downto 0);   -- The B Input 
     OPCODE : in unsigned(2 downto 0); -- Op code entered into ALU 
     RES :in std_logic;    -- The reset pin 
     Q : out signed(7 downto 0)   -- The Output of LU 
     ); 
end lu;         -- End Entity 


architecture Behavioral of lu is 

signal Reg1,Reg2,Reg3 : signed(7 downto 0) := (others => '0'); --The signal declaration 

begin 

Reg1 <= A;  -- Linking Reg1 Signal to Input A 
Reg2 <= B;  -- Linking Reg2 Signal to Input B 
Q <= Reg3;  -- Linking Output Q to Signal Reg3 

process(Clk) 

begin 

    if(rising_edge(Clk)) then -- Calculate at the positive edge of clk 
     case OPCODE is 

      when "000" => 
       Reg3 <= Reg1 + Reg2; -- Output is = to addition 

      when "001" => 
       Reg3 <= Reg1 - Reg2; -- Output is = to subtraction 

      when "010" => 
       Reg3 <= not Reg1;  -- Output is = to NOT gate 

      when "011" => 
       Reg3 <= Reg1 nand Reg2; -- Output is = to NAND gate 

      when "100" => 
       Reg3 <= Reg1 nor Reg2; -- Output is = to NOR gate 

      when "101" => 
       Reg3 <= Reg1 and Reg2; -- Output is = to AND gate 

      when "110" => 
       Reg3 <= Reg1 or Reg2; -- Output is = to OR gate 

      when "111" => 
       Reg3 <= Reg1 xor Reg2; -- Output is = to XOR gate 


      when others =>    -- If anyother Input Outputs nothing 
       NULL; 

     end case;  
    end if; 

end process;  

end Behavioral;

来源

2013-10-31 Jack.S

在什么情况下你想ALU使用移位寄存器，并实现什么功能？你可以用各种不同的方式连接它，但你需要更精确地定义函数 –

假设你的意思是逻辑操作添加到所提供的ALU代码，你需要做出两个改变：

1）在端口列表中，增加你的opcode信号的宽度，使您可以添加新的操作码的值：

OPCODE: in unsigned(3 downto 0); -- Operation selection for the ALU

2）在你的case语句，只需添加新的条件和执行逻辑的代码操作：

case OPCODE is 
     ... 

     when "1000" => 
      Reg3 <= Reg1 srl to_integer(Reg2); -- Reg3 <= Reg1 shifted Reg2 bits to the right 
     when "1001" => 
      Reg3 <= Reg1 sll to_integer(Reg2); -- Reg3 <= Reg1 shifted Reg2 bits to the left 
     when "1010" => 
      Reg3 <= Reg1 ror to_integer(Reg2); -- Reg3 <= Reg1 rotated Reg2 bits to the right 
     when "1011" => 
      Reg3 <= Reg1 rol to_integer(Reg2); -- Reg3 <= Reg1 rotated Reg2 bits to the right 
     when others => 
      Reg3 <= (others => '0'); 
    end case;

来源

2013-11-01 00:57:05 rick

ALU +移位寄存器

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