在七段显示器上写数字的简单流程问题

Question

我是初学者，但仍然不能相信我不能使这么简单的代码工作。 我有Digilent Nexys2 FPGA，编程xilinx ISE 我的目标是在两个不同的七段显示器上打印数字“2”和“1”（我想用我的眼睛看它“21”。A，B，C ，D，E，F，G，P是显示器（kathodes）的LED，AN0和AN1是显示器的阳极，0将它们打开）。

我试图在那里投资的逻辑是，FPGA会很快重复这个'过程'，以至于我的眼睛只能检测到光线。 我认为我应该把clk放在进程敏感列表中的原因是，每当时钟改变时，它都会进入进程并执行我的命令，对吗？ 我在这里犯了什么逻辑错误？ 我试图让如果其他语句如果rising_edge（clk）然后“1”将显示其他“2”，但它仍然导致一些错误..什么？我应该让这个过程时钟？

这里是警告我得到时，我想合成它

WARNING:Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. 

这里是我得到当我尝试生成一个编程位文件警告

WARNING:PhysDesignRules:367 - The signal <clk_IBUF> is incomplete. The signal does not drive any load pins in the design. 
WARNING:Par:288 - The signal clk_IBUF has no load. PAR will not attempt to route this signal. 
WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. 
WARNING:PhysDesignRules:367 - The signal <clk_IBUF> is incomplete. The signal does not drive any load pins in the design. 

和

这里是UCF文件：

NET "clk" LOC = B8; 
NET "A" LOC = L18; 
NET "B" LOC = F18; 
NET "C" LOC = D17; 
NET "D" LOC = D16; 
NET "E" LOC = G14; 
NET "F" LOC = J17; 
NET "G" LOC = H14; 
NET "P" LOC = C17; 
NET "AN0" LOC = F17; 
NET "AN1" LOC = H17; 
NET "AN2" LOC = C18; 
NET "AN3" LOC = F15; 

和来这里的代码本身：

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 

entity disp is 
    Port ( 
     clk : in STD_LOGIC; 
     A : out STD_LOGIC; 
     B : out STD_LOGIC; 
     C : out STD_LOGIC; 
     D : out STD_LOGIC; 
     E : out STD_LOGIC; 
     F : out STD_LOGIC; 
     G : out STD_LOGIC; 
     P : out STD_LOGIC; 
     AN0 : out STD_LOGIC; 
     AN1 : out STD_LOGIC; 
     AN2 : out STD_LOGIC; 
     AN3 : out STD_LOGIC 
    ); 
end disp; 
-- main idea: writing "21" on seven segment display. 
architecture BEHAV of disp is 
begin 
    process (clk) 
    begin 
     --writing '1' (AN0 is on) 
     AN0 <='0'; 
     AN1 <='1'; 
     AN2 <='1'; 
     AN3 <='1'; 
     A <='1'; 
     B <='0'; 
     C <='0'; 
     D <='1'; 
     E <='1'; 
     F <='1'; 
     G <='1'; 
     P <='1'; 
     --writing '2' (AN1 is on) 
     AN0 <='1'; 
     AN1 <='0'; 
     AN2 <='1'; 
     AN3 <='1'; 
     A <='0'; 
     B <='0'; 
     C <='1'; 
     D <='0'; 
     E <='0'; 
     F <='1'; 
     G <='0'; 
     P <='1'; 
    end process; 
end BEHAV; 

Answer 1

因此， Morten先生和Adeel是正确的。 Morten的代码是正确的，但它'发生'如此之快，以至于眼睛无法检测到，所以它看起来像2放在1.所以我加了计数器，这里是代码。

显示数字的速度依赖于恒定的“速度”

这里是主要的代码本身，并等待您的答复（我还能怎么做，使这个简单？）

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 

    entity disp is 
    Port ( 
     SW : in STD_LOGIC; 
     rst : in STD_LOGIC; 
     clk : in STD_LOGIC; 
     led : out STD_LOGIC; 
     A : out STD_LOGIC; 
     B : out STD_LOGIC; 
     C : out STD_LOGIC; 
     D : out STD_LOGIC; 
     E : out STD_LOGIC; 
     F : out STD_LOGIC; 
     G : out STD_LOGIC; 
     P : out STD_LOGIC; 
     AN0 : out STD_LOGIC; 
     AN1 : out STD_LOGIC; 
     AN2 : out STD_LOGIC; 
     AN3 : out STD_LOGIC 
    ); 
    end disp; 

architecture BEHAV of disp is 

    constant bitwidth : integer := 32; 
    constant Speed : integer := 10; 
    signal carry : std_logic_vector (bitwidth downto 0); 
    signal counter, counter_reg : std_logic_vector (bitwidth-1 downto 0) :=(others => '0'); 
    constant value_one : std_logic_vector (bitwidth-1 downto 0) :="00000000000000000000000000000001"; 
    signal drive_an : std_logic :='0'; 

    component adder is 
     Port ( 
      C_in : in STD_LOGIC; 
      A : in STD_LOGIC; 
      B : in STD_LOGIC; 
      C_out : out STD_LOGIC; 
      Sum : out STD_LOGIC; 
      SW : in STD_LOGIC); 
    end component; 

begin 

    carry(0) <= '0'; 
    g_counter: for N in 0 to bitwidth-1 
    generate FOUR_ADDER: adder port map (
     C_in => carry(N), A => counter_reg(N), B => value_one(N), C_out => carry(N+1), Sum => counter(N), SW => SW); 
    end generate;  
    led <= carry(bitwidth); 

    process (clk,rst) begin 
     if rst = '1' then 
      counter_reg <= (others => '0'); 
     elsif rising_edge(clk) then 
      counter_reg <= counter; 
      if counter_reg (Speed)= '1' then 
       drive_an <= not drive_an; 
       counter_reg <= (others => '0'); 
       if drive_an = '0' then 
        AN0 <= '0';   
        AN1 <= '1';   
        AN2 <= '1';   
        AN3 <= '1';   
        A <= '1';   
        B <= '0'; 
        C <= '0';   
        D <= '1';   
        E <= '1';   
        F <= '1';   
        G <= '1';   
        P <= '1'; 
       else 
        AN0 <= '1';   
        AN1 <= '0';   
        AN2 <= '1';   
        AN3 <= '1';   
        A <= '0';   
        B <= '0';   
        C <= '1';   
        D <= '0';   
        E <= '0';   
        F <= '1';   
        G <= '0';   
        P <= '1'; 
       end if; 
      end if;  
     end if; 
    end process; 
end BEHAV; 

如果有人永远都需要对其进行测试： 这里是加法器

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 

entity adder is 
    Port ( 
     C_in : in STD_LOGIC; 
     A : in STD_LOGIC; 
     B : in STD_LOGIC; 
     C_out : out STD_LOGIC;  
     Sum : out STD_LOGIC;  
     SW : in STD_LOGIC 
    ); 
end adder; 


architecture Behavioral of adder is 
begin 
    Sum <= C_in xor (a xor (b xor SW)); 
    C_out <= (a and (b xor SW)) or (C_in and (a xor (b xor SW))); 
end Behavioral; 

这里的代码是UCF文件

NET "clk" LOC = B8; 
NET "A" LOC = L18; 
NET "B" LOC = F18; 
NET "C" LOC = D17; 
NET "D" LOC = D16; 
NET "E" LOC = G14; 
NET "F" LOC = J17; 
NET "G" LOC = H14; 
NET "P" LOC = C17; 
NET "AN0" LOC = F17; 
NET "AN1" LOC = H17; 
NET "AN2" LOC = C18; 
NET "AN3" LOC = F15; 
NET "led" LOC = J14; 

Answer 2

只是把时钟灵敏度名单是不够的。你需要一个if语句

If rising_edge (clk) then --where all assingments here End if;

但是，这是不够的。您还需要更好地计算出七段的更新逻辑。我没有时间，否则我也会告诉你。