VHDL - 时钟边缘外的编码错误

Question

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
use ieee.std_logic_arith.all; 
entity RAM_controler is 
port(
     clk_50 : in std_logic; 
     clk_baud : in std_logic; 
     main_reset : in std_logic; 
     enable: in std_logic; --active high write enable 
     in_data : in std_logic_vector(7 downto 0); 
     W_order : out std_logic; 
     R_order : out std_logic; 
     Data_OUT : out std_logic_vector(7 downto 0); 
     Write_Address_OUT: out std_logic_vector(7 downto 0); 
     Read_Address_OUT: out std_logic_vector(7 downto 0)   
    ); 
end entity RAM_controler; 
architecture Behavioral of RAM_controler is 
type state is (reset,operation); 
signal state_reg,next_state_reg : state; 
signal write_address : std_logic_vector(W-1 downto 0):="00000000"; 
signal next_write_address : std_logic_vector(W-1 downto 0):="00000000";   
begin 
state_change : process(clk_50, main_reset) 
begin 
    if (main_reset = '1') then 
     state_reg <= reset;  
    elsif (rising_edge(clk_50)) then 
     state_reg <= operation; 
     read_counter <= next_read_counter; 
     write_address<= next_write_address; 
     read_address <= next_read_address; 
    end if;  
end process; 

writecounter : process(clk_baud, main_reset,enable) 
begin 
    if (main_reset='1') then 
     next_write_address <= "00000000"; 
     Data_OUT <= "ZZZZZZZZ"; 
     W_order <='0'; 
     Write_Address_OUT <="ZZZZZZZZ"; 
    elsif (rising_edge(clk_baud) and enable='1') then 
     W_order <='1'; 
     Data_OUT <= in_data;    
     Write_Address_OUT <= write_address; 
     if (write_address = "11111111") then 
      next_write_address <= "00000000"; 
     else 
      next_write_address <= write_address+1; 
     end if; 
    else 
     W_order <='0'; 
     Write_Address_OUT <= "ZZZZZZZZ"; 
     next_write_address <= write_address+1; 
    end if; 
end process;   
end Behavioral; 

上面的代码描述了RAM控制器。

使问题的部分是“elsif（rising_edge（clk_baud）和enable ='1'）then”。

错误：不能老是为“Write_Address_OUT”间寄存器在RAM_controler.vhd因为它没有保持时钟边沿

我不`吨知道为什么这一点是错误以外的价值。

有人向我提出建议吗？

谢谢！

Answer 1

如果你的编码顺序逻辑，明智的做法是坚持一个模板。这里就是这样的一个模板，时序逻辑与异步重置，所有的综合工具应该明白：

process(clock, async_reset) -- nothing else should go in the sensitivity list 
begin 
    -- never put anything here 
    if async_reset ='1' then -- or '0' for an active low reset 
     -- set/reset the flip-flops here 
     -- ie drive the signals to their initial values 
    elsif rising_edge(clock) then -- or falling_edge(clock) 
     -- put the synchronous stuff here 
     -- ie the stuff that happens on the rising or falling edge of the clock 
    end if; 
    -- never put anything here 
end process;   

所以使不应该在敏性列表，它不应该在同一个if语句作为测试异步复位和时钟测试。

为什么你收到此错误的原因：

Error : Can`t inter register for "Write_Address_OUT" at RAM_controler.vhd because it does not hold its value outside the clock edge

是因为在你的代码的最后三位分配：

  W_order <='0'; 
      Write_Address_OUT <= "ZZZZZZZZ"; 
      next_write_address <= write_address+1; 

可以在时钟或的下降沿发生（因为你也有在您的灵敏度列表中启用），而不依赖于任何时钟。逻辑合成器不能合成像那样的逻辑。如果你坚持这个模板，你就不会遇到这种问题（这让你更仔细地考虑你期望合成器合成的逻辑）。

所以，我会编码的writecounter过程中更是这样的：

writecounter : process(clk_baud, main_reset) 
begin 
    if (main_reset='1') then 
     next_write_address <= "00000000"; 
     Data_OUT <= "ZZZZZZZZ"; 
     W_order <='0'; 
     Write_Address_OUT <="ZZZZZZZZ"; 
    elsif rising_edge(clk_baud) then 
     if enable='1' then 
      W_order <='1'; 
      Data_OUT <= in_data;    
      Write_Address_OUT <= write_address; 
      if (write_address = "11111111") then 
       next_write_address <= "00000000"; 
      else 
       next_write_address <= write_address+1; 
      end if; 
     else 
      W_order <='0'; 
      Write_Address_OUT <= "ZZZZZZZZ"; 
      next_write_address <= write_address+1; 
     end if; 
    end if; 
end process;   

不过，我要强调的是我的代码不完全一样你的。我不知道你的设计意图，所以我只能猜测你的意图。如果你打算采取其他行为，那么你将不得不实施。无论您的设计意图如何，我坚持使用模板的建议都很重要。

Answer 2

最后else在你的代码实际上应该是：

elsif (rising_edge(clk_baud) and enable='0') then