VHDL - 将std_logic_vector移位8位

Question

既然我在写入时设法移动了文本，我想实现另一个功能，即每秒滚动文本1位。例如，我将从键盘写入“STACK”，然后当我切换一个引脚时，它将在七段显示器上开始浮动。我得到了多个时钟错误，正如我所料。现在，我用计数器解决了这个错误，但文本没有正确滚动，随机字符出现在随机位置。

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 
use IEEE.numeric_std.all; 

entity my_shifter is 
     port(clk  : in std_logic; 
      doShift : in std_logic;--shift mode 
      Scan_Dav : in std_logic;--from keyboard module, new data 
      Data_in : in std_logic_vector (7 downto 0);--scancode of the key pressed 
      O1 : out std_logic_vector(7 downto 0); 
      O2 : out std_logic_vector(7 downto 0); 
      O3 : out std_logic_vector(7 downto 0); 
      O4 : out std_logic_vector(7 downto 0) 
      ); 
end my_shifter; 

architecture bhv of my_shifter is 

signal bytes : std_logic_vector(63 downto 0):=(others => '0'); 
signal Scan_Dav_Sync: std_logic_vector(1 downto 0):="00"; 
signal Previous_Scan_Dav: std_logic:='0'; 
signal shift : std_logic:='0'; 
signal flag : std_logic:='0'; 
signal first_letter: std_logic_vector(7 downto 0):="00000000"; 
begin 
    process(clk) 
     variable var:integer range 0 to 50000000 :=0; 
     begin 
      if rising_edge(clk) then 
       if var = 50000000 then 
        var:=0; 
        flag<='0'; 
        shift <= '1'; 
       else 
        flag <= '1'; 
        var:=var+1; 
        shift <= '0'; 
       end if; 
      end if; 
    end process; 

    process (clk, doShift) 
     begin 
      case doShift is 

       when '0' => 
        if rising_edge(clk) then 
         Scan_Dav_Sync(0) <= Scan_Dav; 
         Scan_Dav_Sync(1) <= Scan_Dav_Sync(0); 
         Previous_Scan_Dav <= Scan_Dav_Sync(1); 
         if (Previous_Scan_Dav = '0') and (Scan_Dav_Sync(1) = '1') then 
          bytes <= bytes (bytes'high-8 downto 0) & Data_in; 
         end if; 
        end if;--till here it works fine. 

       when '1' => -- this is where it messes up 
        if (shift = '1' and flag = '0') then 
         first_letter <= bytes(bytes'high downto bytes'high-7); 
         bytes <= bytes (bytes'high-8 downto 0) & first_letter; 
        end if; 

       when others =>--ignore here 
        bytes <= bytes (bytes'high-8 downto 0) & Data_in; 

      end case; 
    end process; 
    O1 <= bytes(31 downto 24); 
    O2 <= bytes(23 downto 16); 
    O3 <= bytes(15 downto 8); 
    O4 <= bytes(7 downto 0); 
end bhv; 

我不知道我怎样才能解决这个问题？错误在哪里或哪里？

Answer 1

如果你让你的第二个过程成为一个理智的钟控过程，那么很有可能你会摆脱这种工作。

喜欢的东西：

process (clk) 
begin 
    if rising_edge(clk) then 
     case doShift is 
      when '0' => 
       Scan_Dav_Sync(0) <= Scan_Dav; 
       Scan_Dav_Sync(1) <= Scan_Dav_Sync(0); 
       Previous_Scan_Dav <= Scan_Dav_Sync(1); 
       if (Previous_Scan_Dav = '0') and (Scan_Dav_Sync(1) = '1') then 
        bytes <= bytes (bytes'high-8 downto 0) & Data_in; 
       end if; 

      when '1' => 
       if (shift = '1' and flag = '0') then 
        first_letter <= bytes(bytes'high downto bytes'high-7); 
        bytes <= bytes (bytes'high-8 downto 0) & first_letter; 
       end if; 

      when others => 
       bytes <= bytes (bytes'high-8 downto 0) & Data_in; 

     end case; 
    end if; 
end process;