2017-10-13 82 views
-1

我想在vhdl中使用modelsim制作fsm,但是当我尝试编译我的代码时这个错误错误:D:/velilog/bubu.vhd(3):在“clock_in”附近:(vcom-1576)期待END

enter code here 
entity timer_50Mhz is 
    generic(count : integer range 0 to 50000000 := 2);  
     clock_in : in STD_LOGIC; 
      clock_out : out STD_LOGIC); 
end timer_50Mh 
z; 
architecture Behavioral of timer_50Mhz is 
begin 
process(clock_in) 
variable temp :integer range 0 to 5000000 := 0; 
begin 
    if(rising_edge(clock_in)) then 
    if(temp = count-1) then 
    temp :=0; 
    clock_out <='1'; 
    else 
    temp := temp + 1; 
    clock_out <='0'; 
end process; 

end Behavioral; 

如果你能解决它,我将不胜感激。

+0

提供[MCVE]。它意味着完整的代码和测试平台。 – Staszek

+0

只是一个简单的错字这个... – JHBonarius

回答

0

entity timer_50Mhz is 
    generic(count : integer range 0 to 50000000 := 2);  
     clock_in : in STD_LOGIC; 
     clock_out : out STD_LOGIC); 
end timer_50Mhz; 

应该是这样的:

entity timer_50Mhz is 
    generic(count : integer range 0 to 50000000 := 2);  
    port(
     clock_in : in STD_LOGIC; 
     clock_out : out STD_LOGIC); 
end timer_50Mhz; 
+0

非常感谢你! :D ^^ b –