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我正在实施Booth算法，用于将VHDL中的两个数字（无符号2的补码形式）相乘。不幸的是，我对VHDL很穷，无法弄清楚我的错在哪里。
的问题：通过模拟步进，我注意到，当我已经分配的“1011”的值Y，信号MULT了“0UUU”。我不明白为什么会发生。这里是我的代码：VHDL信号分配导致未初始化状态
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- x, y are the n bit numbers to be multiplied.
-- The Algorithm :
-- U = 0, prev_bit = 0;
-- for i = 1 to n do
-- if start of a string of 1's in Y then U = U - X
-- if end of a string of 1's in Y then U = U + X
-- Arithmetic right shift UV
-- Circular right shift Y and copy Y(0) to prev_bit
entity booth is
generic(N : natural := 4);
port(
x, y : in std_logic_vector(N-1 downto 0);
result : out std_logic_vector(2*N-1 downto 0);
clk : in std_logic
);
end booth;
architecture booth_arch of booth is
--temp is equivalent to UV where UV is the result.
signal temp : std_logic_vector(2*N-1 downto 0) := (others => '0');
--prev_bit to compare for starting and ending of strings of 1's.
signal prev_bit : std_logic := '0';
signal mult : std_logic_vector(N-1 downto 0);
begin
process(x, y)
begin
mult <= y;
prev_bit <= '0';
for i in 0 to N-1 loop
if(mult(0) = '1' and prev_bit = '0') then --start of a string of 1's
temp(2*N-1 downto N) <= std_logic_vector(unsigned(temp(2*N-1 downto N)) + unsigned(not(x)) + 1);
elsif(mult(0) = '0' and prev_bit = '1') then --end of a string of 1's
temp(2*N-1 downto N) <= std_logic_vector(unsigned(temp(2*N-1 downto N)) + unsigned(x));
end if;
prev_bit <= mult(0);
mult(N-2 downto 0) <= mult(N-1 downto 1); --circular right shift y.
mult(N-1) <= prev_bit;
temp(2*N-2 downto 0) <= temp(2*N-1 downto 1); --arithmetic right shift temp.
end loop;
result <= temp;
end process;
end booth_arch;
P.S：clk信号在这里是多余的。我还没有用过它。