我写了下面的VHDL代码,它是快速加法器的组成部分。快速加法器由一个8by8寄存器组成,该寄存器连接到代码如下的加法器。我如何消除在Read_Adress中的使用。我想要Read_Adress出std_logic_vector不inout?如何消除vhdl Adder的信号?
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
Entity Adder is
port(
Clock_50_MHZ :in std_logic;
En :in std_logic;
Data_Registerfile : in std_logic_vector(7 downto 0);
Read_Address: inout std_logic_vector(2 downto 0) := "000";
Output : out std_logic_vector(11 downto 0)
);
end Adder;
Architecture arch of Adder is
Signal result : unsigned (11 downto 0):="000000000000";
Signal regData: std_logic_vector(7 downto 0);
Begin
regData <= Data_Registerfile;
Process(Clock_50_MHZ)
Begin
if rising_edge(Clock_50_MHZ) then
if (En = '1') then
if(Read_Address = "000") then
result <= "000000000000" + unsigned(regData);
Read_Address <= Read_Address + 1;
elsif(Read_Address = "111") then
Output <= std_logic_vector(result + unsigned(regData));
Read_Address <= "000";
else
result <= result + unsigned(regData);
Read_Address <= Read_Address + 1;
end if;
end if;
end if;
End Process;
end arch;
谢谢。它解决了它奇妙! – Ivan
您可以将此端口声明为缓冲区,并可以将输出用作信号。 – Khanh
@KhanhDang我正在使用的综合工具不会接受,但这是一个好主意;如何将它作为另一个答案? – Owen