ALU verilog测试台不确定是否正确初始化

Question

我试图为我的ALU写测试台，但是我是初学者。我只是不确定它的写作方式是否正常。例如，我应该使用dut还是uut？并且我是否正确初始化了我的输入？输出波直线不会随着每个位X和一个0而改变。任何见解都将不胜感激。

module Alu_test(); 
    reg [7:0]pc; 
    reg [3:0] CCRin; 
    reg rst,clk; 
    reg [3:0] opcode; 
    reg[7:0] ra; 
    reg[7:0] rb; 
    reg [7:0] in_port; 
    reg[7:0] SP;   //= 255 
    wire[7:0] SP_out; 
    wire [7:0] out_port; 
    wire[255:0] dmem; 
    wire[7:0] ra_out; 
    wire[7:0] rb_out; 
    wire [3:0] CCRo; 
    wire [7:0] npc; 


ALU dut(opcode,ra,rb,ra_out,rb_out,rst,clk,pc,npc,CCRin,CCRo,SP,SP_out,in_port,out_port,dmem); 
initial 
begin 
rst = 0; 
clk = 0; 
opcode = 0; 
SP = 255; 
CCRin = 0; 
pc = 0; 
in_port = 0; 
ra = 0; 
rb = 0; 
#5 
forever 
    #5 clk = ~clk; 

#50 

#5 opcode[3:0] = 4'b0000; //nop 


#5 opcode[3:0] = 4'b0100; //add 
ra =1; 
rb =1; 

#5 opcode[3:0] = 4'b0111; //shift left 
ra =1; 
rb =0; 

#5 opcode[3:0] = 4'b1010; //push 
ra =1; 
rb =2; 

end 
endmodule 

这是模块

module ALU(opcode,ra,rb,ra_out,rb_out,rst,clk,pc,npc,CCRin,CCRo,SP,SP_out,in_port,out_port,dmem); 
    wire [7:0] res; // result 
    input wire [7:0]pc; 
    output reg [7:0] npc; 
    input rst,clk; 
    input wire [3:0] opcode; 
    input wire[7:0] ra; 
    input wire[7:0] rb; 
    output reg[7:0] ra_out; 
    output reg[7:0] rb_out; 
    input wire[7:0] SP; // testbench haygebli SP el mafroud yeb2a = 255 
    output reg[7:0] SP_out; 
    input wire [7:0] in_port; 
    output reg [7:0] out_port; 

    output reg[255:0] dmem; 

    input wire [3:0] CCRin; 
    output reg [3:0] CCRo; 
    wire co; 
    wire cin; 

    wire [7:0] result; //total result 

always @(posedge clk) 
    begin 
    SP_out = SP; 
end 

    assign result = alu_out(ra,rb,cin); 
    assign res = result[1:0]; 
    assign co = result[2]; 



    function [8:0] alu_out; 
    input [1:0] ra,rb; 
    input cin; 

    case (opcode) 
    0: ; 
    4: assign alu_out = ra + rb; 
    5: assign alu_out = ra - rb; 
    6: assign alu_out = ~(ra & rb); 
    7: assign alu_out = {ra[7:0],cin}; 
    8: assign alu_out = {ra[0],cin,ra[7:1]}; 
    10: if (ra == 1) 
      begin 
     dmem[SP_out] = rb; 
     SP_out = SP_out-1; 
     end 
    else 
     begin 
     SP_out = SP_out +1; 
     rb_out = dmem[SP_out]; 
    end 
    11: assign out_port = ra; 
    12: assign ra_out = in_port; 
    13: assign ra_out = rb; 
    default: begin 
    alu_out = 8'bxxxxxxxx; 


end 
endcase 
endfunction 
    always@(posedge clk) 
    begin 
    if (res == 0) 
    CCRo[0] = 1; 
    else if (res < 0) 
    CCRo[1] = 1; 
    else if (co == 1) 
    CCRo[2] = 1; 
    else if (res < 0 & res > result) 
    CCRo[3] = 1; 
    else 
    CCRo = CCRin; 
    if (res) 
    ra_out = res; 

    npc = pc+1; 
end 
endmodule 

Answer 1

使用dut作为实例名称是罚款。如果您愿意，您也可以使用uut。

您应该将时钟世代移动到它自己的initial块中，然后在原始initial块的末尾调用$finish。这应该让你更进一步。现在，4个信号成为众所周知：

initial begin 
    rst = 0; 
    opcode = 0; 
    SP = 255; 
    CCRin = 0; 
    pc = 0; 
    in_port = 0; 
    ra = 0; 
    rb = 0; 
    #5; 
    #50; 
    #5 opcode[3:0] = 4'b0000; //nop 
    #5 opcode[3:0] = 4'b0100; //add 
    ra =1; 
    rb =1; 
    #5 opcode[3:0] = 4'b0111; //shift left 
    ra =1; 
    rb =0; 
    #5 opcode[3:0] = 4'b1010; //push 
    ra =1; 
    rb =2; 
    $finish; 
end 

initial begin 
    clk = 0; 
    forever #5 clk = ~clk; 
end 

你dmem初始化为X.您需要在操作码开车= 10将其设置为其他值。