Verilog测试平台

Question

我想写我自己的测试平台，但它没有给我一个输出。我尽我所能，但没有帮助。任何人都可以帮我一把吗？

module direct(clk, reset, x, y); 
input clk, reset; 
input signed [7:0]x; 
output signed [23:0]y; 
reg signed [23:0]y; 
reg signed [15:0]a[0:8]; //coeff 
reg signed [7:0]rej[0:8]; //reg 
reg signed [23:0]acc; 
reg [4:0]count; // 

always@(posedge clk) 
begin: states 
    parameter s0=0, s1=1, s2=2, s3=3; 
    reg[1:0] state; 
    integer i; 
    if(reset == 0) begin 
     state <= s0; 
    end 
    else begin 

    case(state) 
     s0: begin 
      state <= s1; 
      acc <= 0; 
      a[0] <= 16'd887; 
      a[1] <= 16'd553; 
      a[2] <= -16'd2563; 
      a[3] <= -16'd8745; 
      a[4] <= 16'd19757; 
      a[5] <= -16'd8745; 
      a[6] <= -16'd2563; 
      a[7] <= 16'd553; 
      a[8] <= 16'd887; 
      for (i=0; i<9; i=i+1) 
       rej[i] <= 0; 
      end 

     s1: begin 
      state <= s2; 
      count <= 0; 
      acc <= 0; 
      rej[0]<= x; 
      for (i = 1; i <9; i=i+1) 
       rej[i] <= rej[i-1]; 
      end 

     s2: begin 
      if(count ==9) 
       state <= s3; 
      else 
       begin 
        state <= s2; 
        count <= count + 1'd1; 
        acc <= acc + rej[count]*a[count]; 
       end 
      end 

     s3: begin 
      state <= s1; 
      y <= acc; 
      end 
      default:state <=s0; 
     endcase 
    end 
end 
endmodule 

我自己的测试平台：（如果有人能指出我做错了什么）

`timescale 1 ns/100 ps 
module direct_test(); 
reg clk, reset; 
reg [7:0]x; 
wire [23:0]y; 

    direct U1(
      .clk(clk), 
      .reset(reset), 
      .x(x), 
      .y(y) 
      ); 
    always 
    #10 clk = ~clk; 
    initial 
    begin 
    clk = 1'b0; 
    #5 reset <= 1'b0; 
    x <= 1'd1; 
    #10 reset <= 1'b1; 
end 
endmodule 

Answer 1

还有就是direct模块中的编译错误。改变：

for (i = 1; i <9; i=i+1) rejestry 

到：

for (i = 1; i <9; i=i+1) 

的direct_test模块中的always块防止模拟无法完成。添加$finish到initial块：

initial 
    begin 
    clk = 1'b0; 
    #5 reset <= 1'b0; 
    x <= 1'd1; 
    #10 reset <= 1'b1; 
    #5000 $finish; 
end 

有了这些变化，我看到了从X到 'h377，' h5a0波形y变化等