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我已经使用D-lATCh实现了进位选择加法器。但我得到以下错误。位置关联不能跟随命名关联
HDLCompiler:720 - "/home/aabhinav/Downloads/Example/CSA_4bits/CSA_BEC1.vhd" Line 76: Positional association cannot follow named association
ERROR:HDLCompiler:854 - "/home/aabhinav/Downloads/Example/CSA_4bits/CSA_BEC1.vhd" Line 41: Unit ignored due to previous errors.
下面是我附上的代码。如果任何人都可以帮助我，因为我是VHDL的新手和我的学校项目。
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:08:00 11/16/2016
-- Design Name:
-- Module Name: CSA_BEC1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CSA_BEC1 is
port(A,B : in std_logic_vector(3 downto 0);
cin : in std_logic;
Scsa : out std_logic_vector(4 downto 0));
end CSA_BEC1;
architecture Behavioral of CSA_BEC1 is
COMPONENT d_latch_top is
port(A : in std_logic_vector(4 downto 0);
EN : IN STD_LOGIC;
B : out std_logic_vector(4 downto 0));
end COMPONENT;
COMPONENT MUX10_5 is
PORT(X, Y: in std_logic_vector(4 downto 0);
sel: in std_logic;
m: out std_logic_vector(4 downto 0));
end COMPONENT;
component rc_adder
Port (X : in STD_LOGIC_VECTOR (3 downto 0);
Y : in STD_LOGIC_VECTOR (3 downto 0);
-- Cin: in STD_LOGIC ;
sum : out STD_LOGIC_VECTOR (3 downto 0);
Carry : out STD_LOGIC);
end component;
signal RCSum: STD_LOGIC_VECTOR(3 DOWNTO 0);
signal BECSum, M: STD_LOGIC_VECTOR(4 DOWNTO 0);
signal RCCarry,BECCarry: STD_LOGIC;
signal RC_S_C: STD_LOGIC_VECTOR(4 DOWNTO 0);
begin
RC: rc_adder PORT MAP(X => A, Y => B, SUM => RCSum, Carry => RCCarry);
RC_S_C <= RCCarry&RCSum;
dlatch: d_latch_top PORT MAP(A => RC_S_C,B => BECSum, EN = '1');
MUX: MUX10_5 PORT MAP(X => BECSum, y => RC_S_C , sel => cin, m => Scsa);
end Behavioral;
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:19:36 11/16/2016
-- Design Name:
-- Module Name: rc_adder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rc_adder is
port( X : in std_logic_vector(3 downto 0); --4 bit input 1
Y : in std_logic_vector(3 downto 0); -- 4 bit input 2
-- Cin : in STD_LOGIC;
sum : out std_logic_vector(3 downto 0); -- 4 bit sum
carry : out std_logic -- carry out.
);
end rc_adder;
architecture logic of rc_adder is
COMPONENT full_adder is
port (a : in std_logic;
b : in std_logic;
cin : in std_logic;
sum : out std_logic;
carry : out std_logic
);
end COMPONENT;
signal C0: STD_LOGIC_VECTOR(2 DOWNTO 0);
begin
FA1: full_adder PORT MAP(X(0),Y(0),'0',sum(0),C0(0));
FA2: full_adder PORT MAP(X(1),Y(1),C0(0),sum(1),C0(1));
FA3: full_adder PORT MAP(X(2),Y(2),C0(1),sum(2),C0(2));
FA4: full_adder PORT MAP(X(3),Y(3),C0(2),sum(3),Carry);
end logic;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity d_latch_top is
Port (A : in std_logic_vector(4 downto 0);
EN : in STD_LOGIC;
B : out std_logic_vector(4 downto 0));
end d_latch_top;
architecture Behavioral of d_latch_top is
signal DATA : std_logic_vector(4 downto 0);
begin
DATA <= A when (EN = '1') else DATA;
B <= DATA;
end Behavioral;
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:54:06 11/12/2016
-- Design Name:
-- Module Name: MUX10_5 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MUX10_5 is
PORT(X, Y: in std_logic_vector(4 downto 0);
sel: in std_logic;
m: out std_logic_vector(4 downto 0));
end MUX10_5;
architecture logic of MUX10_5 is
component MUX6_3 is
PORT(sel: in std_logic;
X, Y: in std_logic_vector(2 downto 0);
m: out std_logic_vector(2 downto 0));
end component;
component MUX4_2 is
PORT(sel, X0, X1, Y0, Y1: in std_logic;
m0, m1: out std_logic);
end component;
begin
mux6_3_inst0 : MUX6_3
PORT MAP(sel => sel, X => X(2 downto 0), Y => Y(2 downto 0),
m => m(2 downto 0));
mux4_2_inst0 : MUX4_2
PORT MAP(sel => sel, X0 => X(3), X1 => X(4), Y0 => Y(3), Y1 => Y(4),
m0 => m(3), m1 => m(4));
end logic;
我们不是您的个人调试服务。 –
这不是一个[MCVE] - 你可以有用地修剪几页不必要的注释掉的东西，并把它放到几行。我不打算通过这个混乱找到第76行。 –