library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Lab3_Adder1 is
Port (cin : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
s : out STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC);
end Lab3_Adder1;
architecture Behavioral of Lab3_Adder1 is
SIGNAL c : STD_LOGIC_VECTOR (4 DOWNTO 0);
begin
c(0) <= cin;
s <= a XOR b XOR c (3 DOWNTO 0);
c (4 DOWNTO 1) <= (a AND b) OR (a AND c(3 DOWNTO 0)) OR (b AND c(3 DOWNTO 0));
cout <= c(4);
end Behavioral;
你好,这是我第一次使用这个论坛。我在VHDL上做了华莱士树乘法。上面的代码是完整加法器的代码。我想知道我们如何在主代码中调用函数/组件? (如在C编程中)。我会在我的主代码中调用这个完整的加法器。 vhdl乘法器