Verilog测试台状态图

Question

我有一个家庭作业问题，需要制作一个mealy机器的状态图，每当连续输入3个或更多个1时就会输出一个状态图。 我想出了它，并且我看到它的方式在我的案例（状态）中概述，并且我感觉它是正确的，因为它编译得很好。我认为我的问题在于我的测试平台。这一切都在一个文件中，但打散，使我的解释更容易...

// This is my module for the state diagram 
module prob558(output reg y,input x, clk,reset); 
parameter s0=2'b00,s1=2'b01,s2=2'b10,s3=2'b11; 
reg [1:0] state; 
always @(posedge clk, negedge reset) 
if (reset==0) state<=s0; 
else 
case(state) 
s0: if (x==0) state<=s0 && y==0; else if(x==1)state<=s1 && y==0; 
s1: if (x==0) state<=s0 && y==0; else if(x==1)state<=s2 && y==0; 
s2: if (x==0) state<=s0 && y==0; else if(x==1)state<=s3 && y==0; 
s3: if (x==0) state<=s0 && y==1; else if(x==1)state<=s3 && y==1; 
endcase 
endmodule 

这里是我的测试台开始的地方......我想在这里做的是只输出x和y来看到他们来出什么是

module prob558_tb(); 
reg clock; 
reg reset; 
reg x; 
wire y; 
prob558 p558(y,x,clk,reset); 


// this is where I am starting to get lost, I am only trying to follow a 
// poorly explained example my professor showed us for a synchronous 
// circuit... 
initial #200 $finish; 
initial begin 
clock = 0; 
reset = 0; 
#5 reset =1; 
#5 clock=~clock; 
end 

// This I came up with my own, and although it is wrong, this is the way I am 
// thinking of it. What I am trying to do below is to have the 'x' inputs be 
// set by these numbers I am inputting, and then I was thinking it would go 
// through my case statements and the 'y' output would be given 
initial begin 
#10 x=1; 
#10 x=0; 
#10 x=1; 
#10 x=1; 
#10 x=1; 
#10 x=1; 
#10 x=1; 
#10 x=0; 
#10 x=0; 
end 

// the following below I know is correct! 
initial begin 
$monitor("x= %d y=%d",x,y); 
$dumpfile("prob558.vcd"); 
$dumpvars; 
end 
endmodule 

我得到的0101010 X输入和我的Y输出全部出来为“Y = X” 如果任何人有任何提示改进我将不胜感激！

Answer 1

这里有一对夫妇，我想在指向您的测试平台，并帮助你找出什么是错在你的RTL代码更正：

1. clk必须clock

   // prob558 p558(y,x,clk,reset); <-- clk must be clock 
       prob558 p558(y,x,clock,reset); 
   

2. clock世代必须处于无限循环

   //#5 clock=~clock; <-- should be inside an infinite loop 
   
   initial begin 
       forever begin 
       #5 clock = ~clock; 
       end 
   end 
   

3. 等待复位断言某些输入信号之前

   @(posedge reset); // wait for reset 
   

4. 使用@(posedge clock)而不是#10同步您输入clock使用非阻塞分配。

   // #10 x=1; <-- use @(posedge clock) instead and a non-blocking assignment 
   // #10 x=0; 
   // #10 x=1; 
   // #10 x=1; 
   // #10 x=1; 
   // #10 x=1; 
   // #10 x=1; 
   // #10 x=0; 
   // #10 x=0; 
       @(posedge clock) x <= 1; 
       @(posedge clock) x <= 0; 
       @(posedge clock) x <= 1; 
       @(posedge clock) x <= 1; 
       @(posedge clock) x <= 1; 
       @(posedge clock) x <= 1; 
       @(posedge clock) x <= 1; 
       @(posedge clock) x <= 0; 
       @(posedge clock) x <= 0; 
   

你可能想尝试运行上述更正here，看到波形。

现在，您可以尝试修复RTL代码的逻辑（输出y输出不正确，请参阅Greg的评论），因为这是您的作业。