Verilog测试平台代码

任何人都可以帮我写下面代码的verilog测试平台代码！我有尝试，但它是行不通的！Verilog测试平台代码

module top(clock_in, Reset, Hold, up_down, Led_Out, f);  
    input clock_in, Reset, Hold, up_down; 
    output  [6:0] Led_Out;   
    output wire [3:0] f; 

    wire pulse; 

    clock_design temp0(clock_in, pulse); 
    up_down_counter temp1(pulse, Reset, Hold, up_down, f); 
    led7 temp2(Led_Out, f); 
endmodule

LED7：

module led7(iOut, iQ); 
    output reg [6:0] iOut; 
    input  [3:0] iQ; 

    always @(iQ) 
    case (iQ) 
     4'b0000: iOut = 7'b0000001; //0 
     4'b0001: iOut = 7'b1001111; //1 
     4'b0010: iOut = 7'b0010010; //2 
     4'b0011: iOut = 7'b0000110; //3 
     4'b0100: iOut = 7'b1001100; //4 
     4'b0101: iOut = 7'b0100100; //5 
     4'b0110: iOut = 7'b0100000; //6 
     4'b0111: iOut = 7'b0001111; //7 
     4'b1000: iOut = 7'b0000000; //8 
     4'b1001: iOut = 7'b0000100; //9 
     default: iOut = 7'b0000000; //default 
    endcase 
    endmodule

up_down_counter：

module up_down_counter (Clock,Reset,Hold,up_down,Q); 
    input Clock,Reset,Hold,up_down; 
    output reg [3:0] Q; 
    integer direction; 


    always @(posedge Clock) 
    begin 
     if(up_down) 
     direction = 1; 
     else 
     direction = -1; 

    if (!Reset && direction == 1) 
     Q <= 0; 
     else if(!Reset && direction == -1) 
     Q <= 1001; 
     else if (!Hold)   
     Q <= Q + direction; 

     if (direction==1 && Q[0]==1 && Q[1]==0 &&Q[1]==0 && Q[3]==1) 
     Q <= 0; 
     else if (direction==-1 && Q[0]==0 && Q[1]==0 &&Q[2]==0 && Q[3]==0) 
     Q <= 1001; 
     end 
    endmodule

clock_design：

module clock_design (clock_in,clock_out); 
    input clock_in; 
    output clock_out; 
    parameter which_clock=1; 
    reg [31:0] divided_clocks=0; 

    always @(posedge clock_in) 
    divided_clocks = divided_clocks +1; 

    assign clock_out = divided_clocks[which_clock]; 
endmodule

我的测试台代码

module counter_tb; 
    reg [6:0] Led_Out_tb; 
    wire [3:0] f_tb; 
    reg clock_in_tb, Reset_tb, Hold_tb, up_down_tb; 

    top dut(clock_in_tb, Reset_tb,Hold_tb, up_down_tb, Led_Out_tb, f_tb); 

    initial begin 
    #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1; 
    #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1; 
    #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1; 
    #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1; 
    #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1; 
    #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1; 
    #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1; 
    #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1; 
    #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1; 
    #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1; 
    #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1; 
    #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1; 
    #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1; 
    #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1; 
    #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1; 
    #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1; 
    #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1; 
    #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1; 
    #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1; 
    #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1; 
    #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1; 
    #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1; 
    #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1; 
    #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1; 
    #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1; 
    #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 1; 
    #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0; 
    #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0; 
    #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0; 
    #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0; 
    #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0; 
    #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0; 
    #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0; 
    #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0; 
    #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0; 
    #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0; 
    #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0; 
    #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0; 
    #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0; 
    #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0; 
    #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0; 
    #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0; 
    #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0; 
    #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0; 
    #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0; 
    #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0; 
    #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0; 
    #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0; 
    #10 clock_in_tb = 1;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0; 
    #10 clock_in_tb = 0;Hold_tb = 0;Reset_tb = 1; up_down_tb = 0; 
    end 
endmodule

来源

2013-03-20 Lê Hòa

“不起作用”对您的问题没有用处。 – toolic 2013-03-20 11:53:04

对'divided_clocks'使用非阻塞赋值。 – toolic 2013-03-20 11:55:13

测试平台明智我会成立一个时钟和复位这样的：

reg clk ; //Rising edge every 10 timesteps 
initial begin 
    clk = 0; 
    #5; 
    forever begin 
    #5 clk = ~clk; 
    end 
end 

// TB Reset_tb 
reg Reset_tb 
initial begin 
    Reset_tb = 0; 
    @(posedge clk); 
    @(posedge clk); 
    Reset_tb = 1; 
end

并进行实际测试是这样的：

//The actual test 
initial begin 
    Hold_tb = 0; 
    up_down_tb = 1; 
    repeat (50) begin 
    @(posedge clk); 
    end 
    up_down_tb = 1; 
    repeat (50) begin 
    @(posedge clk); 
    end 
    $finish(); 
end

关于代码

你有一段看起来应该是always @(posedge clk)块中的组合逻辑。

always @(posedge Clock) 
begin 
    if(up_down) 
    direction = 1; 
    else 
    direction = -1;

我想这应该是：

always @* begin 
    if(up_down)begin 
    direction = 1; 
    end 
    else begin 
    direction = -1; 
    end 
end

如果不包括begin end的if语句仅适用于下一行。我会更频繁地使用开始结束，所以你的代码明确地显示了你的意图。

你有下面的一段代码：

if (!Reset && direction == 1) 
    Q <= 0; 
    else if(!Reset && direction == -1) 
    Q <= 1001; 
    else if (!Hold)   
    Q <= Q + direction; 

    if (direction==1 && Q[0]==1 && Q[1]==0 &&Q[1]==0 && Q[3]==1) 
    Q <= 0; 
    else if (direction==-1 && Q[0]==0 && Q[1]==0 &&Q[2]==0 && Q[3]==0) 
    Q <= 1001;

是否有一个4号，如果失踪别的吗？ if (direction==1 && Q[0]==1 && Q[1]==0 &&Q[1]==0 && Q[3]==1)

我会避免在RTL中使用整数类型，因为这往往是矫枉过正，尤其是在这里你只是存储1或-1，真的只需要1位的值。寄存器和电线可以签署：

reg signed signed_reg ; 
reg signed [7:0] signed_reg8;

还可以声明常数签署：

reg_signed = 1'sd-1 ; //1Bit Signed Decimal value -1

我觉得不好的做法，使用大小写混合信号的名字，我总是用小写。常量如参数和localparams都是大写。这使得拼写错误的可能性小一些，你可能花费很多时间试图解决为什么某些东西不能正常工作，那么你意识到其中一个连接使用小写而不是大写第一个字符。

来源

2013-03-20 09:32:14 Morgan

Verilog测试平台代码

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