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我收到以下错误司的Verilog与测试
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警告：产品vcscompiler_Net（723）的许可证将在 26天内到期：o：31-Dec-2015。如果您想临时禁用此消息，请将vcs LIC EXPIRE WARNING环境变为 ，此消息到期前的天数为 start（最小值为0）。解析设计文件 '../src/divi .V' 错误 - [SE]语法错误 “继Verilog源有语法错误
.../src目录/迪维.V”，12：令牌是“位'reg [4：0]位;
系统verilog关键字'位'预计不会在此 上下文中使用。 1个错误CPU时间：0.143秒编译CHI-SV R-0：/类/ LINUX/avicente/ASIC_Design /工作>
module streamlined_divider(quotient,remainder,ready,dividend,divider,start,clk);
input [15:0] dividend,divider;
input start, clk;
output [15:0] quotient,remainder;
output ready;
reg [15:0] quotient;
reg [31:0] dividend_copy, divider_copy, diff;
wire [15:0] remainder = dividend_copy[15:0];
reg [4:0] bit;
wire ready = !bit;
initial bit = 0;
always @(posedge clk)
if (ready && start) begin
bit = 16;
quotient = 0;
dividend_copy = {16'd0,dividend};
divider_copy = {1'b0,divider,15'd0};
end else begin
diff = dividend_copy - divider_copy;
quotient = { quotient[14:0], ~diff[31] };
divider_copy = { 1'b0, divider_copy[31:1] };
if (!diff[31]) dividend_copy = diff;
bit = bit - 1;
end
endmodule
module l07_test_div();
wire [15:0] quot, rem;
reg [15:0] shadow_quot, shadow_rem;
reg [15:0] a, b;
integer i;
parameter num_tests = 1000;
reg clk;
initial clk = 0;
always #1 clk = ~clk;
reg start;
wire ready;
wire [15:0] infinity;
assign infinity = 16'hffff;
// simple_divider div(quot,rem,ready,a,b,start,clk);
streamlined_divider div(quot,rem,ready,a,b,start,clk);
initial begin
# 0.5;
while (!ready) #1;
for (i=0; i<num_tests; i=i+1) begin:A
integer shadow_quot, shadow_rem;
a = $random;
b = i & 1 ? $random : $random & 3;
start = 1;
while (ready) #1;
start = 0;
while (!ready) #1;
shadow_quot = b ? a/b : infinity;
shadow_rem = b ? a % b : a;
#1;
if (quot != shadow_quot || rem != shadow_rem) begin
$display("Wrong quot: %h/%h = %h r %h != %h r %h (correct)",
a, b, quot, rem, shadow_quot, shadow_rem);
$stop;
end
end
$display("Tried %d divide tests",num_tests);
$stop;
end
endmodule'
需要帮助辩别错误