比较器的Verilog测试平台错误

我是Verilog的新手，当a等于，小于，大于b时，我需要制作一个8位比较器。下面是我的代码（这使我没有任何错误）：比较器的Verilog测试平台错误

module MagnitudeComparator8bit (input signed [7:0]a, 
           input signed [7:0]b, 
           output eq, 
           output lt, 
           output gt); 
    assign eq = a == b; 
    assign lt = a < b; 
    assign gt = a > b; 
endmodule

这里就是我的测试平台，但是当我运行模拟，我碰上了多个错误，但我不知道我错了。任何帮助？

module MagnitudeComparatorTestbench; 
    reg [7:0] a, b; 
    wire eq, lt, gt; 

    MagnitudeComparator8bit uut(
     .a(a), 
     .b(b), 
     .eq(eq), 
     .lt(lt), 
     .gt(gt) 
    ); 

    initial begin 
      $monitor (“%d %b %b %d %d %d”, $time, a, b, eq, lt, gt); 
      a=8’b11110000; 
      b=8’b11110000; 
     #10 a=8’b1001001; 
      b=8’b10101010; 
     #10 a=8’b11001100; 
      b=8’b10101000; 
     #10 $finish 
    end 
endmodule

错误：

testbench.sv:14: error: unmatched character (hex ?) 
testbench.sv:e: error: unmatched character (hex ?) 
testbench.sv:e: error: unmatched character (hex ?) 
testbench.sv:e: syntax error 
testbench.sv:e: error: unmatched character (hex ?) 
testbench.sv:e: error: unmatched character (hex ?) 
testbench.sv:e: error: unmatched character (hex ?) 
testbench.sv:e: error: malformed statement 
testbench.sv:f: error: unmatched character (hex ?) 
testbench.sv:f: error: unmatched character (hex ?) 
testbench.sv:f: error: unmatched character (hex ?) 
testbench.sv:f: syntax error 
testbench.sv:f: error: malformed statement 
testbench.sv:10: error: unmatched character (hex ?) 
testbench.sv:10: error: unmatched character (hex ?) 
testbench.sv:10: error: unmatched character (hex ?) 
testbench.sv:10: syntax error 
testbench.sv:10: error: malformed statement 
testbench.sv:11: error: unmatched character (hex ?) 
testbench.sv:11: error: unmatched character (hex ?) 
testbench.sv:11: error: unmatched character (hex ?) 
testbench.sv:11: syntax error 
testbench.sv:11: error: malformed statement 
testbench.sv:12: error: unmatched character (hex ?) 
testbench.sv:12: error: unmatched character (hex ?) 
testbench.sv:12: error: unmatched character (hex ?) 
testbench.sv:12: syntax error 
testbench.sv:12: error: malformed statement 
testbench.sv:13: error: unmatched character (hex ?) 
testbench.sv:13: error: unmatched character (hex ?) 
testbench.sv:13: error: unmatched character (hex ?) 
testbench.sv:13: syntax error 
testbench.sv:13: error: malformed statement 
testbench.sv:14: error: unmatched character (hex ?) 
testbench.sv:14: error: unmatched character (hex ?) 
testbench.sv:14: error: unmatched character (hex ?) 
testbench.sv:14: syntax error 
testbench.sv:14: error: malformed statement 
testbench.sv:16: syntax error 
Exit code expected: 0, received: 40

来源

2016-01-28 smd

您的帖子奇怪引号字符。在我复制和粘贴你的代码后，这些给了我错误。我修正了报价。复制此代码：

module MagnitudeComparatorTestbench; 
    reg [7:0] a, b; 
    wire eq, lt, gt; 

    MagnitudeComparator8bit uut(
     .a(a), 
     .b(b), 
     .eq(eq), 
     .lt(lt), 
     .gt(gt) 
    ); 

    initial begin 
      $monitor ("%d %b %b %d %d %d", $time, a, b, eq, lt, gt); 
      a=8'b11110000; 
      b=8'b11110000; 
     #10 a=8'b1001001; 
      b=8'b10101010; 
     #10 a=8'b11001100; 
      b=8'b10101000; 
     #10 $finish; 
    end 
endmodule

我也在$完成后添加了一个半。

来源

2016-01-29 00:32:10 toolic

我试过你的代码，唯一的问题是$完成后缺少分号。所以＃10 $完成;

来源

2016-01-29 00:35:25 DBB

比较器的Verilog测试平台错误

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